[PATCH] D103629: [AArch64] Cost-model i8 vector loads/stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> And while we don't have a load instruction that supports this

If `<4 x i8>` loads matter, we should probably convert them to a 32-bit load followed by a zip1, which should would have a cost of 2.  (Or possibly 3 on big-endian, I guess.)  Basically the inverse of LowerTruncateVectorStore.


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https://reviews.llvm.org/D103629