[PATCH] D103256: [AArch64] Remove SETCC of CSEL when the latter's condition can be inverted

Thu Jun 3 08:09:10 PDT 2021

joechrisellis accepted this revision.
joechrisellis added a comment.
This revision is now accepted and ready to land.

LGTM, one small suggestion.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15329-15332
+  if (Cond == ISD::SETNE && isOneConstant(RHS) &&
+      LHS->getOpcode() == AArch64ISD::CSEL &&
+      isNullConstant(LHS->getOperand(0)) && isOneConstant(LHS->getOperand(1)) &&
+      LHS->hasOneUse()) {
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Untested, but you might be able to simplify this a little bit with LLVM's pattern matching functionality. See: https://llvm.org/doxygen/PatternMatch_8h_source.html.

It might not work, though. If not I'm fine with this. 😄 

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103256/new/

https://reviews.llvm.org/D103256