[PATCH] D103602: [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson created this revision.
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Register allocation may spill virtual registers to the stack, which can
increase alignment requirements of the stack frame. If the the function
did not require stack realignment before register allocation, the
registers required to do so may not be reserved/available. This results
in a stack frame that requires realignment but can not be realigned.

Instead, only increase the alignment of the stack if we are still able
to realign.

The register SpillAlignment will be ignored if we can't realign, and the
backend will be responsible for emitting the correct unaligned loads and
stores. This seems to be the assumed behaviour already, e.g.
ARMBaseInstrInfo::storeRegToStackSlot and X86InstrInfo::storeRegToStackSlot
are both `canRealignStack` aware.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103602

Files:
  llvm/lib/CodeGen/VirtRegMap.cpp
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
  llvm/test/CodeGen/Thumb2/mve-phireg.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/AMX/amx-across-func.ll
  llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/AMX/amx-spill.ll
  llvm/test/CodeGen/X86/addsub-constant-folding.ll
  llvm/test/CodeGen/X86/avx-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/avx-vzeroupper.ll
  llvm/test/CodeGen/X86/avx512-bugfix-25270.ll
  llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/X86/fma.ll
  llvm/test/CodeGen/X86/half.ll
  llvm/test/CodeGen/X86/rotate-extract-vector.ll
  llvm/test/CodeGen/X86/sext-vsetcc.ll
  llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll
  llvm/test/CodeGen/X86/stack-folding-int-avx512.ll
  llvm/test/CodeGen/X86/vec-libcalls.ll
  llvm/test/CodeGen/X86/vec-strict-128.ll
  llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/X86/vector-half-conversions.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
  llvm/test/CodeGen/X86/vzero-excess.ll

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