[PATCH] D103597: [AArch64] Modified AArch64LoadStoreOptimizer to generate STP instructions for memcpys

[Meera Nakrani via Phabricator via llvm-commits]

MeeraN added a comment.

Hi Sjoerd,

I can definitely add a comment in and some more information to the description as well in order to explain in more detail what is going on. I will also add a MIR test as well.

In D103597#2795765 <https://reviews.llvm.org/D103597#2795765>, @SjoerdMeijer wrote:

> Ideally we want to generate a LDP and STP for the test cases that you added. Why do we not yet get the LDP?

We don't get the LDP since it fails at the very start of this function (called on line 1529) since FirstMI is a load instruction:

   static bool
   canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
                    SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
                    const TargetRegisterInfo *TRI) {
     if (!FirstMI.mayStore())
       return false;
  
     ...
  }

Because this returns false, the renaming of registers isn't attempted for the loads and so they don't get recognised as a pair. It is something I still need to look into in more detail to see if there is something else we can try.


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