[PATCH] D103601: [CostModel][AArch64] Add tests for ctlz, ctpop and cttz. NFC.

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


================
Comment at: llvm/test/Analysis/CostModel/AArch64/ctlz.ll:67
+
+define <8 x i64> @test_ctlz_v8i64(<8 x i64> %a) {
+; CHECK-LABEL: 'test_ctlz_v8i64'
----------------
This tests a 8 x 64 = 256 bit vector, which is already bigger than the vector register.


================
Comment at: llvm/test/Analysis/CostModel/AArch64/ctlz.ll:76
+
+define <16 x i64> @test_ctlz_v16i64(<16 x i64> %a) {
+; CHECK-LABEL: 'test_ctlz_v16i64'
----------------
And this tests a 512 bit vector. Having this tests here won't hurt anyone, but I don't think it adds much compared to the previous tests, so might as well remove this one.


================
Comment at: llvm/test/Analysis/CostModel/AArch64/ctlz.ll:112
+
+define <16 x i32> @test_ctlz_v16i32(<16 x i32> %a) {
+; CHECK-LABEL: 'test_ctlz_v16i32'
----------------
Same for this one.


================
Comment at: llvm/test/Analysis/CostModel/AArch64/ctlz.ll:191
+  ret <16 x i8> %ctlz
+}
+
----------------
You could consider adding a 32 x i8 case here, i.e. a test/vector that is bigger than the register width. 


================
Comment at: llvm/test/Analysis/CostModel/AArch64/ctpop.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=aarch64 -cost-model -analyze | FileCheck %s
----------------
And similar remarks here about the vector widths as in the previous file.


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Comment at: llvm/test/Analysis/CostModel/AArch64/ctpop.ll:4
+
+; Verify the cost of scalar ctpop intstructions.
+
----------------
Nit, typo: `intstructions`


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https://reviews.llvm.org/D103601