[PATCH] D103552: Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, evandro, HsiangKai, arcbbb, khchen, rogfer01.
Herald added subscribers: mstorsjo, StephenFan, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
Herald added a project: LLVM.

The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register. This patch attempts to work around this.

-For unmasked .wv, add a special TIED pseudo that pretends like
 the first operand and the destination must be the same register. This
 disables the earlyclobber for that source. Mark the instruction
 as convertible to 3 address form which will switch it to the
 original untied pseudo when the TwoAddressInstructionPass decides
 that keeping them tied would require an extra copy. This uses
 code in RISCVInstrInfo.cpp to do the conversion to the untied
 opcode.

The untie test case show that we can generate the untied version.
Not sure it was profitable to do it in this case, but they have
really simple IR.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103552

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

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