[PATCH] D103269: [RISCV] Reserve an emergency spill slot for any RVV spills

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir:1
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple riscv64 -mattr=+experimental-v -start-before=prologepilog -o - \
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frasercrmck wrote:
> HsiangKai wrote:
> > I am not sure what is the difference between update_llc_test_checks.py and update_mir_test_checks.py. I see most of the MIR tests are updated by update_mir_test_checks.py. Just curious why this file is updated by update_llc_test_checks.py.
> I'm not 100% on this, but I believe `update_mir_test_checks.py` will only add checks to the MIR, like when coming from `-run-pass` or `-stop-after`. You still need `update_llc_test_checks.py` if you want to check the asm.
> 
> This particular test was copied from `out-of-each-emergency-slot.mir` which checks the resulting asm.
Got it. Thanks for your explanation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103269/new/

https://reviews.llvm.org/D103269