[PATCH] D103510: [RISCV] Use vmv.v.v if we know COPY is under the same vl and vtype.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, rogfer01, frasercrmck.
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If we know the source operand of COPY is defined by a vector instruction
with tail agnostic and the same LMUL and there is no vsetvli between
COPY and the define instruction to change the vl and vtype, we could use
vmv.v.v or vmv.v.i to copy vector registers to get better performance than
the whole vector register move instructions.

This patch only considers all these instructions within one basic block.

Case 1:
bb.0:

  ...
  VSETVLI          # The first VSETVLI before COPY.
  ...              # Use the VSETVLI to check LMUL and tail agnostic.
  ...
  vy = VOP va, vb  # Define vy.
  ...              # There is no vsetvli to change vl and vtype between
  ...              # VOP and COPY.
  vx = COPY vy

Case 2:
bb.0:

  ...
  VSETVLI          # The first VSETVLI before COPY.
  ...              # Use the VSETVLI to check LMUL and tail agnostic.
  ...
  vy = VOP va, vb  # Define vy.
  ...              # There is no vsetvli to change vl and vtype between
  ...              # VOP and COPY.
  VSETVLI          # This vsetvli will not change vl and vtype of the first one.
  ...
  vx = COPY vy


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103510

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll