[PATCH] D103105: [AArch64] Optimise bitreverse lowering in ISel

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6887
+    REVB = DAG.getNode(AArch64ISD::REV32, DL, VST, Op.getOperand(0));
+
+    break;
----------------
You can probably remove some of this extra whitespace.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103105/new/

https://reviews.llvm.org/D103105