[PATCH] D103269: [RISCV] Reserve an emergency spill slot for any RVV spills

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D103269#2792890 <https://reviews.llvm.org/D103269#2792890>, @HsiangKai wrote:

> In our downstream implementation, we do not go through SelectBaseAddr for vector load/store to generate ADDI for the base address. In this way, we have no need to reserve one additional scavenging slot for vector load/store.

Don't we also set a flag in RISCVMachineFunctionInfo when we emit a spill/reload?


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https://reviews.llvm.org/D103269