[PATCH] D103211: [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

ShihPo Hung via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 1 18:15:46 PDT 2021

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arcbbb accepted this revision.
arcbbb added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103211/new/

https://reviews.llvm.org/D103211

Previous message: [llvm] 59f44f9 - [RISCV][test] Add new tests of bitwise and with constant for the Zbs extension
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