[PATCH] D103462: [SDAG] allow more cast folding for vector sext-of-setcc

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10846
+          if (User->getOpcode() != ISD::ZERO_EXTEND ||
+              User->getValueType(0) != VT)
+            return false;
----------------
lebedev.ri wrote:
> What if it is extending to the even wider type than `VT`?
It seems neutral whether we have wider or narrower other type - trade a sext of the compare for a zext of the input. This might be because the transform to create zext-loads is conservative about uses.

Let me know if this matches what you have in mind (I can add a test either way):

```
define <8 x i32> @multi_use_wider_size(<8 x i8>* %src, <8 x i16>* %dst) nounwind {
  %load = load <8 x i8>, <8 x i8>* %src
  %zext = zext <8 x i8> %load to <8 x i32>
  %icmp = icmp eq <8 x i8> %load, zeroinitializer
  %sext = sext <8 x i1> %icmp to <8 x i16>
  store <8 x i16> %sext, <8 x i16>* %dst
  ret <8 x i32> %zext
}
```

Currently, we get:

```
vmovq	(%rdi), %xmm1
vpmovzxbd	%xmm1, %ymm0 ; 256-bit return value
vpxor	%xmm2, %xmm2, %xmm2
vpcmpeqb %xmm2, %xmm1, %xmm1
vpmovsxbw %xmm1, %xmm1
vmovdqa	%xmm1, (%rsi) ; 128-bit compare value

```
If we allow type mismatch:

```
vmovq	(%rdi), %xmm1
vpmovzxbd	%xmm1, %ymm0 
vpmovzxbw	%xmm1, %xmm1 
vpxor	%xmm2, %xmm2, %xmm2
vpcmpeqw	%xmm2, %xmm1, %xmm1
vmovdqa	%xmm1, (%rsi)

```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103462/new/

https://reviews.llvm.org/D103462