[PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Ping @craig.topper, just making sure you're okay with this patch as-is before diving into the next stage.

I'm going to start looking into a total-size cap but I think we'll need extra MVTs: with the max supported MVT size of `v128i8` we'd be reducing our legal `i64` vectors from `v256i64` to `v32i64` which feels like a sharp drop.

Perhaps this is something to discuss more broadly with the RISC-V group. What's a sensible max fixed-length size for RVV? We could go on adding new MVTs for a long time until everything gets fed up with us hogging the enum values. 512b vectors? 1Kb? 4Kb? Though I've just checked and an unspecified out-of-tree backend was able to add `v128i32` up to `v2048i32` so maybe there's more wiggle room than I thought.


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  https://reviews.llvm.org/D102493/new/

https://reviews.llvm.org/D102493