[PATCH] D103427: [X86] Fix handling of maskmovdqu in X32

[Harald van Dijk via Phabricator via llvm-commits]

hvdijk created this revision.
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The maskmovdqu instruction has a 32-bit and a 64-bit variant, the former using EDI, the latter RDI, but the use of the register is implicit. In 64-bit mode, a 0x67 prefix can be used to get the version using EDI, but there is no way to express this in assembly in a single instruction, the only way is with an explicit addr32.

This change adds support for the instruction. When generating assembly text, that explicit addr32 will be added. When not generating assembly text, it will be kept as a single instruction and will be emitted with that 0x67 prefix. When parsing assembly text, it will be re-parsed as ADDR32 followed by MASKMOVDQU64, which still results in the correct bytes when converted to machine code.

The same applies to vmaskmovdqu as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103427

Files:
  llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
  llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/test/CodeGen/X86/maskmovdqu.ll
  llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
  llvm/utils/TableGen/X86DisassemblerTables.cpp
  llvm/utils/TableGen/X86RecognizableInstr.cpp

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