[llvm] 63fe4cb - [SDAG] add check to sext-of-setcc fold to bypass changing a legal op

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-05-31T08:58:11-04:00
New Revision: 63fe4cb08206fb973761b8e744bdd5d500c25b8b

URL: https://github.com/llvm/llvm-project/commit/63fe4cb08206fb973761b8e744bdd5d500c25b8b
DIFF: https://github.com/llvm/llvm-project/commit/63fe4cb08206fb973761b8e744bdd5d500c25b8b.diff

LOG: [SDAG] add check to sext-of-setcc fold to bypass changing a legal op

I accidentaly pushed a draft of D103280 that was discussed
during the review, but it was not supposed to be the final
version.

Rather than revert and recommit, I'm updating the existing
code. This way we have a record of the codegen diff that
would result if we decide to remove this predicate in the
future.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/X86/sext-vsetcc.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bffd251195d0..7f49078f2c36 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10941,8 +10941,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
       // Try to eliminate the sext of a setcc by zexting the compare operands.
       // TODO: Handle signed compare by sexting the ops.
       if (!ISD::isSignedIntSetCC(CC) && N0.hasOneUse() &&
-          TLI.isOperationLegalOrCustom(ISD::SETCC, VT) /*&&
-          !TLI.isOperationLegalOrCustom(ISD::SETCC, SVT)*/) {
+          TLI.isOperationLegalOrCustom(ISD::SETCC, VT) &&
+          !TLI.isOperationLegalOrCustom(ISD::SETCC, SVT)) {
         // We have an unsupported narrow vector compare op that would be legal
         // if extended to the destination type. See if the compare operands
         // can be freely extended to the destination type.

diff  --git a/llvm/test/CodeGen/X86/sext-vsetcc.ll b/llvm/test/CodeGen/X86/sext-vsetcc.ll
index 9066b11e8f81..110b04499d20 100644
--- a/llvm/test/CodeGen/X86/sext-vsetcc.ll
+++ b/llvm/test/CodeGen/X86/sext-vsetcc.ll
@@ -417,20 +417,19 @@ define <8 x i32> @cmp_ne_zextload_from_legal_op(<8 x i16>* %x, <8 x i16>* %y) {
 ;
 ; AVX2-LABEL: cmp_ne_zextload_from_legal_op:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX2-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
-; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vmovdqa (%rdi), %xmm0
+; AVX2-NEXT:    vpcmpeqw (%rsi), %xmm0, %xmm0
+; AVX2-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpmovsxwd %xmm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: cmp_ne_zextload_from_legal_op:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX512-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vmovdqa (%rdi), %xmm0
+; AVX512-NEXT:    vpcmpeqw (%rsi), %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogq $15, %zmm0, %zmm0, %zmm0
-; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; AVX512-NEXT:    vpmovsxwd %xmm0, %ymm0
 ; AVX512-NEXT:    retq
   %loadx = load <8 x i16>, <8 x i16>* %x
   %loady = load <8 x i16>, <8 x i16>* %y