[PATCH] D103197: [AMDGPU] All GWS instructions need aligned VGPR on gfx90a
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 27 02:04:35 PDT 2021
rampitec added a comment.
JBTW, this patch directly reflects what's actually happen in HW. Even though these 3 instructions read 32 bit as a source internally they request to read 64 bit which in turn triggered alignment requirement. I assume this is really modeled as "read dword as an operand and have an implicit read of a superreg".
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https://reviews.llvm.org/D103197/new/
https://reviews.llvm.org/D103197
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