[PATCH] D103197: [AMDGPU] All GWS instructions need aligned VGPR on gfx90a
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 26 12:13:47 PDT 2021
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4225-4234
+ // Add implicit aligned super-reg to force alignment on the data operand.
+ const DebugLoc &DL = MI.getDebugLoc();
+ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+ const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
+ Register DataReg = Op->getReg();
+ bool IsAGPR = TRI->isAGPR(MRI, DataReg);
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Should just constrain the register class to an even aligned 32-bit register class
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D103197/new/
https://reviews.llvm.org/D103197
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