[PATCH] D103338: Rename MachineMemOperand::getOrdering -> getSuccessOrdering.

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 28 13:24:29 PDT 2021


efriedma created this revision.
efriedma added a reviewer: jyknight.
Herald added subscribers: foad, kerbowa, pengfei, jfb, jrtc27, fedor.sergeev, hiraditya, nhaehnle, jvesely, arsenm, jholewinski.
efriedma requested review of this revision.
Herald added a project: LLVM.

Since this method can apply to cmpxchg operations, make sure it's clear what value we're actually retrieving.  This will help ensure we don't accidentally ignore the failure ordering of cmpxchg in the future.

We could potentially introduce a getOrdering() method on AtomicSDNode that asserts the operation isn't cmpxchg, but not sure that's worthwhile.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103338

Files:
  llvm/include/llvm/CodeGen/MachineMemOperand.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineStableHash.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/XCore/XCoreISelLowering.cpp

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