[PATCH] D103284: [AArch64][RISCV] Make sure isel correctly honors failure orderings.

[Eli Friedman via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0b3b0a727ad6: [AArch64][RISCV] Make sure isel correctly honors failure orderings. (authored by efriedma).

Changed prior to commit:
  https://reviews.llvm.org/D103284?vs=348377&id=348574#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103284/new/

https://reviews.llvm.org/D103284

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/MachineMemOperand.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp

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