[PATCH] D103334: [GISel] Eliminate redundant bitmasking
Jessica Paquette via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 28 12:25:52 PDT 2021
paquette added inline comments.
================
Comment at: llvm/include/llvm/Target/GlobalISel/Combine.td:650
redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,
- zext_trunc_fold, icmp_to_true_false_known_bits]>;
+ zext_trunc_fold, icmp_to_true_false_known_bits, overlapping_and]>;
----------------
Probably shouldn't be in this group since it doesn't use KnownBits?
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:3008
+
+ // FIXME: This should be removed once GISelKnownBits supports vectors.
+ if (Ty.isVector())
----------------
This doesn't use KnownBits?
(If this was yoinked from somewhere else, then we probably need to update a combine. GISelKnownBits supports vectors nowadays last time I checked.)
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:3025
+ B.buildCopy(Dst, B.buildConstant(Ty, 0));
+ }
+ };
----------------
Minor stylistic suggestion:
```
if (C1 & C2) {
B.buildAnd(...);
return;
}
B.buildCopy(...);
```
Is it actually necessary to emit the copy at all though? You could do
```
Dst = G_CONSTANT iN 0
```
right?
================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -verify-machineinstrs -global-isel=1 | FileCheck %s
----------------
Can this be a MIR test?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D103334/new/
https://reviews.llvm.org/D103334
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