[PATCH] D103291: [AArch64][GISel] and+or+shl => bfi

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:2158
+  case TargetOpcode::G_OR: {
+    /// Look for operations that take the lower `Width=Size-ShiftImm` bits of
+    /// `ShiftSrc` and insert them into the upper `Width` bits of `MaskSrc` via
----------------
Why is this a doxygen comment?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:2190
+    I.eraseFromParent();
+    return constrainSelectedInstRegOperands(BFM, TII, TRI, RBI);
+  }
----------------
I think `emitInstr` handles the constraining for you already:

```
MachineInstr *AArch64InstructionSelector::emitInstr(
...
  constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
  return &*MI;
}
```


================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -verify-machineinstrs -global-isel | FileCheck %s --check-prefixes=CHECK,GISEL
----------------
Is it possible to use a MIR testcase instead?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103291/new/

https://reviews.llvm.org/D103291