[PATCH] D103274: [X86] AMD Zen 3 has fast per-lane variable shuffles

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 28 08:40:15 PDT 2021


RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86.td:1116
+    [FeatureMacroFusion,
+     FeatureFastVariablePerLaneShuffle];
   list<SubtargetFeature> ZN3Tuning =
----------------
If possible I'd make the znver3 change as a followup so its separate from this refactor.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:36023
+  AllowVariablePerLaneMask &=
+      (Depth >= VariablePerLaneShuffleDepth) || HasVariableMask;
   // VPERMI2W/VPERMI2B are 3 uops on Skylake and Icelake so we require a
----------------
We never decided whether to always allow per/cross lane shuffles for avx512 capable targets as they all have decent variable shuffle units (the only case that is bad seems to be KNL's PSHUFB, which we've never cared strongly about.) - which would allow us to clean up a lot of the tests below.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:36097
   // which is much simpler than any shuffle.
-  if (UnaryShuffle && MaskContainsZeros && AllowVariableMask &&
       isSequentialOrUndefOrZeroInRange(Mask, 0, NumMaskElts, 0) &&
----------------
lebedev.ri wrote:
> craig.topper wrote:
> > lebedev.ri wrote:
> > > This one is weird. I'm not sure why fast-ness of variable shuffles matters here.
> > You mean because it's just AND/FAND not a shuffle? Fastness was added to AllowVariableMask later. Initially it was just the depth check. Probably guarding the constant pool?
> > You mean because it's just AND/FAND not a shuffle?
> 
> Yes.
> 
> > Fastness was added to AllowVariableMask later. Initially it was just the depth check. Probably guarding the constant pool?
> 
> Yes, i think so.
Yeah its a legacy thing, and we don't have any good way to gauge the impact of vector constant masks in isel, so we're just a bit cautious :(


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