[PATCH] D103280: [SDAG] try harder to fold casts into vector compare

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10958
+          // TODO: Handle more than one use if the other uses are free to zext.
+          return ISD::isNON_EXTLoad(V.getNode()) &&
+                 ISD::isUNINDEXEDLoad(V.getNode()) &&
----------------
lebedev.ri wrote:
> I think we can also accept `ZEXTLOAD`, since we'd just increase the desired number of leading zeros?
Probably, but I don't have a test example yet for that pattern. So ok to add one more TODO?


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Comment at: llvm/test/CodeGen/X86/sext-vsetcc.ll:420-424
 ; AVX2-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX2-NEXT:    vpcmpeqw (%rsi), %xmm0, %xmm0
 ; AVX2-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpmovsxwd %xmm0, %ymm0
----------------
If we allow widening of a legal type, this test will show it. We would convert to:

```
vpmovzxwd	(%rdi), %ymm0   
vpmovzxwd	(%rsi), %ymm1
vpcmpeqd	%ymm1, %ymm0, %ymm0
vpcmpeqd	%ymm1, %ymm1, %ymm1
vpxor	%ymm1, %ymm0, %ymm0

```
I don't think we can say with certainty that's a win for all targets (although I don't have any non-x86 examples to compare). It's probably ok, but if we want to allow it, then it can be a one-line follow-up patch?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103280/new/

https://reviews.llvm.org/D103280