[PATCH] D103299: [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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All that really matters is that the VLMAX of the preceding
instructions is the same as the VLMAX required by the mask
operation.

Also update the vmsge(u) handling to use the SEW/LMUL we use for
other mask register operations. We were matching it to the compare
before. Some cases will be improve if we fix masked compares to
use tail agnostic policy. I think they ignore the tail policy
anyway.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103299

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

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