[llvm] 020df69 - [RISCV] Fix typo, use addImm instead of addReg.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-05-27T14:04:51-07:00
New Revision: 020df692d801c4fa9a67eb32e923927e33f9e4b5

URL: https://github.com/llvm/llvm-project/commit/020df692d801c4fa9a67eb32e923927e33f9e4b5
DIFF: https://github.com/llvm/llvm-project/commit/020df692d801c4fa9a67eb32e923927e33f9e4b5.diff

LOG: [RISCV] Fix typo, use addImm instead of addReg.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d6a5ef0dd3d5..731aa9833208 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1391,7 +1391,7 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
     uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
         .addReg(VL)
-        .addReg(ShiftAmount);
+        .addImm(ShiftAmount);
     BuildMI(MBB, II, DL, TII->get(RISCV::SUB), VL)
         .addReg(ScaledRegister, RegState::Kill)
         .addReg(VL, RegState::Kill);

diff  --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
index 187f407ce798..0758f7c75419 100644
--- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -304,7 +304,7 @@ define void @lmul_1_2_4_8() nounwind {
 ; CHECK-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 64
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a1, a0, vl
+; CHECK-NEXT:    slli a1, a0, 4
 ; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -64