[PATCH] D103284: [AArch64][RISCV] Make sure isel correctly honors failure orderings.

[Eli Friedman via Phabricator via llvm-commits]

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If a cmpxchg specifies acquire or seq_cst on failure, make sure we generate code consistent with that ordering even if the success ordering is not acquire/seq_cst.

At one point, it was ambiguous whether this sort of construct was valid, but the C++ standad and LLVM now accept arbitrary combinations of success/failure orderings.

This doesn't address the corresponding issue in AtomicExpand.  (This was reported as https://bugs.llvm.org/show_bug.cgi?id=33332 .)

Fixes https://bugs.llvm.org/show_bug.cgi?id=50512.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103284

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/MachineMemOperand.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/utils/TableGen/CodeGenDAGPatterns.cpp

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