[PATCH] D103010: [PowerPC] Export 16 byte load-store instructions

[Kai Luo via Phabricator via llvm-commits]

lkail updated this revision to Diff 348197.
lkail added a comment.

1. Solve `LQ` register constraint `RTp != RA` by adding `early-clobber` on `RTp`
2. Use doubleword load/store to perform quadword restore/spill

`LQ` and `STQ` are still needed for quadword atomic load/store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103010/new/

https://reviews.llvm.org/D103010

Files:
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrFormats.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/PPCSchedule.td
  llvm/test/CodeGen/PowerPC/ldst-16-byte.mir

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