[llvm] 74edfb2 - [AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-05-26T17:01:02-07:00
New Revision: 74edfb28053dac26d82d1372123be03db630ef62

URL: https://github.com/llvm/llvm-project/commit/74edfb28053dac26d82d1372123be03db630ef62
DIFF: https://github.com/llvm/llvm-project/commit/74edfb28053dac26d82d1372123be03db630ef62.diff

LOG: [AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE.

The rules were already there, it just needed re-ordering so the odd case didn't
bail out too early.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 398f1caf769e..08e4ea3c7f78 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -328,7 +328,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
                                  {v4s32, p0, 128, 8},
                                  {v2s64, p0, 128, 8}})
       .clampScalar(0, s8, s64)
-      .lowerIfMemSizeNotPow2()
       .lowerIf([=](const LegalityQuery &Query) {
         return Query.Types[0].isScalar() &&
                Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
@@ -338,6 +337,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampMaxNumElements(0, s16, 8)
       .clampMaxNumElements(0, s32, 4)
       .clampMaxNumElements(0, s64, 2)
+      .lowerIfMemSizeNotPow2()
       .customIf(IsPtrVecPred);
 
   // Constants

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 0b92477f3913..ecd156ff555b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -32,7 +32,7 @@ define i128 @ABIi128(i128 %arg1) {
   ret i128 %res
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1:_(<7 x s32>), %0:_(p0) :: (store 28 into %ir.addr, align 32) (in function: odd_vector)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3:_(<3 x s32>), %4:_(p0) :: (store 12 into %ir.addr + 16, align 16, basealign 32) (in function: odd_vector)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
 define void @odd_vector(<7 x i32>* %addr) {

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 797adc5acb68..634bcb79bc39 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -517,3 +517,26 @@ body: |
     G_STORE %val64(s64), %0(p0) :: (store 2)
     G_STORE %val64(s64), %0(p0) :: (store 4)
 ...
+---
+name:            store_6xs64
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x0
+    ; CHECK-LABEL: name: store_6xs64
+    ; CHECK: liveins: $x0
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+    ; CHECK: %ptr:_(p0) = COPY $x0
+    ; CHECK: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store 16)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+    ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 into unknown-address + 16)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+    ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store 16 into unknown-address + 32)
+    ; CHECK: RET_ReallyLR
+    %val:_(<6 x s64>) = G_IMPLICIT_DEF
+    %ptr:_(p0) = COPY $x0
+    G_STORE %val(<6 x s64>), %ptr(p0) :: (store 48, align 16)
+    RET_ReallyLR
+...