[PATCH] D103185: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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It turned out that DS_GWS opcodes must use even aligned registers.

A separate change is needed to address the issue in codegen.


https://reviews.llvm.org/D103185

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/test/MC/AMDGPU/gfx90a_err.s
  llvm/test/MC/AMDGPU/gfx90a_err_pos.s
  llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
  llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt

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