[PATCH] D103126: [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb2c7ac874f51: [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D103126?vs=347820&id=348009#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103126/new/

https://reviews.llvm.org/D103126

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

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