[PATCH] D103170: [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm created this revision.
peterwaller-arm added reviewers: paulwalker-arm, joechrisellis, bsmith, david-arm, sdesmalen, efriedma, Matt.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
peterwaller-arm requested review of this revision.
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This avoids the use of the vector unit for copying from scalar to
vector. There is an extra ptrue instruction, but a predicate register
with the ptrue pattern populated is likely to be free in the context of
real code.

Tests were generated from a template to cover the cases mentioned at the
top of the test file and should be pretty exhaustive.

Co-authored-by: Francesco Petrogalli <francesco.petrogalli at arm.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103170

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll

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