[llvm] 5f500d7 - [MCA] Add a test for PR50483. NFC
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Wed May 26 07:53:28 PDT 2021
Author: Andrea Di Biagio
Date: 2021-05-26T15:52:11+01:00
New Revision: 5f500d73cd1aaff4c9ab2fd5c327c2d5ca9ae5c9
URL: https://github.com/llvm/llvm-project/commit/5f500d73cd1aaff4c9ab2fd5c327c2d5ca9ae5c9
DIFF: https://github.com/llvm/llvm-project/commit/5f500d73cd1aaff4c9ab2fd5c327c2d5ca9ae5c9.diff
LOG: [MCA] Add a test for PR50483. NFC
Added:
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
Modified:
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
new file mode 100644
index 000000000000..207b0358cfb6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=5 -noalias=false < %s | FileCheck %s
+
+# PR50483: Execution of loads and stores should not overlap if flag -noalias is set to false.
+
+str x1, [x4]
+ldr x2, [x4]
+
+# CHECK: Iterations: 5
+# CHECK-NEXT: Instructions: 10
+# CHECK-NEXT: Total Cycles: 9
+# CHECK-NEXT: Total uOps: 10
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 1.11
+# CHECK-NEXT: IPC: 1.11
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 1.00 * str x1, [x4]
+# CHECK-NEXT: 1 3 1.00 * ldr x2, [x4]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - CortexA55UnitALU
+# CHECK-NEXT: [0.1] - CortexA55UnitALU
+# CHECK-NEXT: [1] - CortexA55UnitB
+# CHECK-NEXT: [2] - CortexA55UnitDiv
+# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
+# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
+# CHECK-NEXT: [4] - CortexA55UnitFPDIV
+# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
+# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
+# CHECK-NEXT: [6] - CortexA55UnitLd
+# CHECK-NEXT: [7] - CortexA55UnitMAC
+# CHECK-NEXT: [8] - CortexA55UnitSt
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x4]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x4]
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeeE. . str x1, [x4]
+# CHECK-NEXT: [0,1] .DeeE. . ldr x2, [x4]
+# CHECK-NEXT: [1,0] .DeeeE . str x1, [x4]
+# CHECK-NEXT: [1,1] . DeeE . ldr x2, [x4]
+# CHECK-NEXT: [2,0] . DeeeE . str x1, [x4]
+# CHECK-NEXT: [2,1] . DeeE . ldr x2, [x4]
+# CHECK-NEXT: [3,0] . DeeeE. str x1, [x4]
+# CHECK-NEXT: [3,1] . DeeE. ldr x2, [x4]
+# CHECK-NEXT: [4,0] . DeeeE str x1, [x4]
+# CHECK-NEXT: [4,1] . DeeE ldr x2, [x4]
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 5 0.0 0.0 0.0 str x1, [x4]
+# CHECK-NEXT: 1. 5 0.0 0.0 0.0 ldr x2, [x4]
+# CHECK-NEXT: 5 0.0 0.0 0.0 <total>
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