[PATCH] D103105: [AArch64] Optimise bitreverse lowering in ISel

[Irina Dobrescu via Phabricator via llvm-commits]

Rin marked an inline comment as done.
Rin added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6872
+    return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU,
+                               true);
+  }
----------------
SjoerdMeijer wrote:
> Nit: `/*OverrideNEON=*/true` ?
> 
> And we don't need the curly brackets for this if.
Should I get rid of the 
```
/*OverrideNEON=*/true
```

above in LowerCTTZ as well?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6879
+    REVB = DAG.getNode(AArch64ISD::REV32, DL, MVT::v16i8, Op.getOperand(0));
+  if (VT.getScalarSizeInBits() == 64)
+    REVB = DAG.getNode(AArch64ISD::REV64, DL, MVT::v16i8, Op.getOperand(0));
----------------
SjoerdMeijer wrote:
> then this can be an `else`.
changed it to switch statements


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103105/new/

https://reviews.llvm.org/D103105