[PATCH] D103105: [AArch64] Optimise bitreverse lowering in ISel

[Irina Dobrescu via Phabricator via llvm-commits]

Rin added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6869
+
+  if (VT.isScalableVector() ||
+      useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)) {
----------------
SjoerdMeijer wrote:
> How about these SVE checks, do we need tests for that?
I think those are already tested for. That's just old code for the SVE case that I put here to make sure I don't change anything for SVE


Repository:
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  https://reviews.llvm.org/D103105/new/

https://reviews.llvm.org/D103105