[llvm] 8c86161 - [NFC][X86] clang-format X86TTIImpl::getInterleavedMemoryOpCostAVX2()
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed May 26 02:31:57 PDT 2021
Author: Roman Lebedev
Date: 2021-05-26T12:27:47+03:00
New Revision: 8c86161a0be2266dd9232e9f1c13b625c2ff0db2
URL: https://github.com/llvm/llvm-project/commit/8c86161a0be2266dd9232e9f1c13b625c2ff0db2
DIFF: https://github.com/llvm/llvm-project/commit/8c86161a0be2266dd9232e9f1c13b625c2ff0db2.diff
LOG: [NFC][X86] clang-format X86TTIImpl::getInterleavedMemoryOpCostAVX2()
I plan to make changes to it, and undoing formatting each time is not going to be fun.
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 838a1baa15a5a..eef1e07e15176 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4760,8 +4760,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
// TODO: Support also strided loads (interleaved-groups with gaps).
if (Indices.size() && Indices.size() != Factor)
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
- Alignment, AddressSpace,
- CostKind);
+ Alignment, AddressSpace, CostKind);
// VecTy for interleave memop is <VF*Factor x Elt>.
// So, for VF=4, Interleave Factor = 3, Element type = i32 we have
@@ -4773,8 +4772,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
// (see MachineValueType.h::getVectorVT()).
if (!LegalVT.isVector())
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
- Alignment, AddressSpace,
- CostKind);
+ Alignment, AddressSpace, CostKind);
unsigned VF = VecTy->getNumElements() / Factor;
Type *ScalarTy = VecTy->getElementType();
@@ -4791,8 +4789,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
EVT ETy = TLI->getValueType(DL, VT);
if (!ETy.isSimple())
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
- Alignment, AddressSpace,
- CostKind);
+ Alignment, AddressSpace, CostKind);
// TODO: Complete for other data-types and strides.
// Each combination of Stride, element bit width and VF results in a
diff erent
@@ -4802,39 +4799,39 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
// The cost of the loads/stores is accounted for separately.
//
static const CostTblEntry AVX2InterleavedLoadTbl[] = {
- { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64
+ {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64
- { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8
- { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
- { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
- { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8
- { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8
+ {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8
+ {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8
+ {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8
+ {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
+ {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8
- { 3, MVT::v8i32, 17 }, //(load 24i32 and)deinterleave into 3 x 8i32
+ {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32
- { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
- { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
- { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
- { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8
- { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8
+ {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8
+ {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8
+ {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8
+ {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8
+ {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8
- { 8, MVT::v8i32, 40 } //(load 64i32 and)deinterleave into 8 x 8i32
+ {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
};
static const CostTblEntry AVX2InterleavedStoreTbl[] = {
- { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store)
-
- { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store)
- { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
- { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store)
- { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store)
- { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store)
-
- { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store)
- { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
- { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store)
- { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store)
- { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store)
+ {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store)
+
+ {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store)
+ {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store)
+ {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store)
+ {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
+ {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)
+
+ {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store)
+ {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store)
+ {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store)
+ {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store)
+ {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store)
};
if (Opcode == Instruction::Load) {
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