[PATCH] D102739: [RISCV] Enable cross basic block aware vsetvli insertion

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 347850.
craig.topper added a comment.

Add MIR tests and some more interesting ll tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102739/new/

https://reviews.llvm.org/D102739

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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