[llvm] 8cc437a - [ARM] Extra predicated tests for VMULH. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue May 25 14:24:19 PDT 2021
Author: David Green
Date: 2021-05-25T22:24:06+01:00
New Revision: 8cc437a8a16e6d2dd403a9a3a74594574e3371d4
URL: https://github.com/llvm/llvm-project/commit/8cc437a8a16e6d2dd403a9a3a74594574e3371d4
DIFF: https://github.com/llvm/llvm-project/commit/8cc437a8a16e6d2dd403a9a3a74594574e3371d4.diff
LOG: [ARM] Extra predicated tests for VMULH. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/mve-vmulh.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmulh.ll b/llvm/test/CodeGen/Thumb2/mve-vmulh.ll
index a214eeae590a2..af8dd335198f7 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmulh.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmulh.ll
@@ -540,3 +540,427 @@ vector.body: ; preds = %vector.body, %entry
for.cond.cleanup: ; preds = %vector.body
ret void
}
+
+
+define void @vmulh_s32_pred(i32* noalias nocapture %d, i32* noalias nocapture readonly %x, i32* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_s32_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: blt .LBB18_3
+; CHECK-NEXT: @ %bb.1: @ %vector.ph
+; CHECK-NEXT: add.w r12, r3, #3
+; CHECK-NEXT: mov.w lr, #1
+; CHECK-NEXT: bic r12, r12, #3
+; CHECK-NEXT: sub.w r12, r12, #4
+; CHECK-NEXT: add.w r12, lr, r12, lsr #2
+; CHECK-NEXT: dls lr, r12
+; CHECK-NEXT: .LBB18_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vctp.32 r3
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vldrwt.u32 q1, [r1], #16
+; CHECK-NEXT: vmov.f32 s0, s4
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vldrwt.u32 q2, [r2], #16
+; CHECK-NEXT: vmov.f32 s12, s8
+; CHECK-NEXT: subs r3, #4
+; CHECK-NEXT: vmov.f32 s2, s5
+; CHECK-NEXT: vmov.f32 s14, s9
+; CHECK-NEXT: vmov r12, s0
+; CHECK-NEXT: vmov r4, s12
+; CHECK-NEXT: vmov.f32 s16, s6
+; CHECK-NEXT: vmov.f32 s18, s7
+; CHECK-NEXT: vmov.f32 s4, s10
+; CHECK-NEXT: vmov.f32 s6, s11
+; CHECK-NEXT: vmullb.s32 q2, q1, q4
+; CHECK-NEXT: smmul r12, r4, r12
+; CHECK-NEXT: vmov r4, s9
+; CHECK-NEXT: vmov q1[2], q1[0], r12, r4
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: vmov r4, s14
+; CHECK-NEXT: smmul r12, r4, r12
+; CHECK-NEXT: vmov r4, s11
+; CHECK-NEXT: vmov q1[3], q1[1], r12, r4
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vstrwt.32 q1, [r0], #16
+; CHECK-NEXT: le lr, .LBB18_2
+; CHECK-NEXT: .LBB18_3: @ %for.cond.cleanup
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: pop {r4, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 3
+ %n.vec = and i32 %n.rnd.up, -4
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> poison)
+ %2 = sext <4 x i32> %wide.masked.load to <4 x i64>
+ %3 = getelementptr inbounds i32, i32* %y, i32 %index
+ %4 = bitcast i32* %3 to <4 x i32>*
+ %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %4, i32 4, <4 x i1> %active.lane.mask, <4 x i32> poison)
+ %5 = sext <4 x i32> %wide.masked.load12 to <4 x i64>
+ %6 = mul nsw <4 x i64> %5, %2
+ %7 = lshr <4 x i64> %6, <i64 32, i64 32, i64 32, i64 32>
+ %8 = trunc <4 x i64> %7 to <4 x i32>
+ %9 = getelementptr inbounds i32, i32* %d, i32 %index
+ %10 = bitcast i32* %9 to <4 x i32>*
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %8, <4 x i32>* %10, i32 4, <4 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 4
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+define void @vmulh_u32_pred(i32* noalias nocapture %d, i32* noalias nocapture readonly %x, i32* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_u32_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: blt .LBB19_3
+; CHECK-NEXT: @ %bb.1: @ %vector.ph
+; CHECK-NEXT: dlstp.32 lr, r3
+; CHECK-NEXT: .LBB19_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vldrw.u32 q0, [r1], #16
+; CHECK-NEXT: vmov.f32 s8, s2
+; CHECK-NEXT: vldrw.u32 q3, [r2], #16
+; CHECK-NEXT: vmov.f32 s16, s14
+; CHECK-NEXT: vmov.f32 s10, s3
+; CHECK-NEXT: vmov.f32 s18, s15
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: vmullb.u32 q1, q4, q2
+; CHECK-NEXT: vmov.f32 s14, s13
+; CHECK-NEXT: vmullb.u32 q2, q3, q0
+; CHECK-NEXT: vmov.f32 s0, s9
+; CHECK-NEXT: vmov.f32 s1, s11
+; CHECK-NEXT: vmov.f32 s2, s5
+; CHECK-NEXT: vmov.f32 s3, s7
+; CHECK-NEXT: vstrw.32 q0, [r0], #16
+; CHECK-NEXT: letp lr, .LBB19_2
+; CHECK-NEXT: .LBB19_3: @ %for.cond.cleanup
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 3
+ %n.vec = and i32 %n.rnd.up, -4
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i32, i32* %x, i32 %index
+ %1 = bitcast i32* %0 to <4 x i32>*
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> poison)
+ %2 = zext <4 x i32> %wide.masked.load to <4 x i64>
+ %3 = getelementptr inbounds i32, i32* %y, i32 %index
+ %4 = bitcast i32* %3 to <4 x i32>*
+ %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %4, i32 4, <4 x i1> %active.lane.mask, <4 x i32> poison)
+ %5 = zext <4 x i32> %wide.masked.load12 to <4 x i64>
+ %6 = mul nuw <4 x i64> %5, %2
+ %7 = lshr <4 x i64> %6, <i64 32, i64 32, i64 32, i64 32>
+ %8 = trunc <4 x i64> %7 to <4 x i32>
+ %9 = getelementptr inbounds i32, i32* %d, i32 %index
+ %10 = bitcast i32* %9 to <4 x i32>*
+ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %8, <4 x i32>* %10, i32 4, <4 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 4
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+define void @vmulh_s16_pred(i16* noalias nocapture %d, i16* noalias nocapture readonly %x, i16* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_s16_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: it lt
+; CHECK-NEXT: poplt {r7, pc}
+; CHECK-NEXT: .LBB20_1: @ %vector.ph
+; CHECK-NEXT: add.w r12, r3, #7
+; CHECK-NEXT: mov.w lr, #1
+; CHECK-NEXT: bic r12, r12, #7
+; CHECK-NEXT: sub.w r12, r12, #8
+; CHECK-NEXT: add.w r12, lr, r12, lsr #3
+; CHECK-NEXT: dls lr, r12
+; CHECK-NEXT: .LBB20_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vctp.16 r3
+; CHECK-NEXT: vpstt
+; CHECK-NEXT: vldrht.u16 q0, [r1], #16
+; CHECK-NEXT: vldrht.u16 q1, [r2], #16
+; CHECK-NEXT: vmullt.s16 q2, q1, q0
+; CHECK-NEXT: vmullb.s16 q0, q1, q0
+; CHECK-NEXT: subs r3, #8
+; CHECK-NEXT: vshr.u32 q2, q2, #16
+; CHECK-NEXT: vshr.u32 q0, q0, #16
+; CHECK-NEXT: vmovnt.i32 q0, q2
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vstrht.16 q0, [r0], #16
+; CHECK-NEXT: le lr, .LBB20_2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 7
+ %n.vec = and i32 %n.rnd.up, -8
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i16, i16* %x, i32 %index
+ %1 = bitcast i16* %0 to <8 x i16>*
+ %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
+ %2 = sext <8 x i16> %wide.masked.load to <8 x i32>
+ %3 = getelementptr inbounds i16, i16* %y, i32 %index
+ %4 = bitcast i16* %3 to <8 x i16>*
+ %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %4, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
+ %5 = sext <8 x i16> %wide.masked.load12 to <8 x i32>
+ %6 = mul nsw <8 x i32> %5, %2
+ %7 = lshr <8 x i32> %6, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %8 = trunc <8 x i32> %7 to <8 x i16>
+ %9 = getelementptr inbounds i16, i16* %d, i32 %index
+ %10 = bitcast i16* %9 to <8 x i16>*
+ call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %8, <8 x i16>* %10, i32 2, <8 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 8
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+define void @vmulh_u16_pred(i16* noalias nocapture %d, i16* noalias nocapture readonly %x, i16* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_u16_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: it lt
+; CHECK-NEXT: poplt {r7, pc}
+; CHECK-NEXT: .LBB21_1: @ %vector.ph
+; CHECK-NEXT: add.w r12, r3, #7
+; CHECK-NEXT: mov.w lr, #1
+; CHECK-NEXT: bic r12, r12, #7
+; CHECK-NEXT: sub.w r12, r12, #8
+; CHECK-NEXT: add.w r12, lr, r12, lsr #3
+; CHECK-NEXT: dls lr, r12
+; CHECK-NEXT: .LBB21_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vctp.16 r3
+; CHECK-NEXT: vpstt
+; CHECK-NEXT: vldrht.u16 q0, [r1], #16
+; CHECK-NEXT: vldrht.u16 q1, [r2], #16
+; CHECK-NEXT: vmullt.u16 q2, q1, q0
+; CHECK-NEXT: vmullb.u16 q0, q1, q0
+; CHECK-NEXT: subs r3, #8
+; CHECK-NEXT: vshr.u32 q2, q2, #16
+; CHECK-NEXT: vshr.u32 q0, q0, #16
+; CHECK-NEXT: vmovnt.i32 q0, q2
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vstrht.16 q0, [r0], #16
+; CHECK-NEXT: le lr, .LBB21_2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 7
+ %n.vec = and i32 %n.rnd.up, -8
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i16, i16* %x, i32 %index
+ %1 = bitcast i16* %0 to <8 x i16>*
+ %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
+ %2 = zext <8 x i16> %wide.masked.load to <8 x i32>
+ %3 = getelementptr inbounds i16, i16* %y, i32 %index
+ %4 = bitcast i16* %3 to <8 x i16>*
+ %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %4, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)
+ %5 = zext <8 x i16> %wide.masked.load12 to <8 x i32>
+ %6 = mul nuw <8 x i32> %5, %2
+ %7 = lshr <8 x i32> %6, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %8 = trunc <8 x i32> %7 to <8 x i16>
+ %9 = getelementptr inbounds i16, i16* %d, i32 %index
+ %10 = bitcast i16* %9 to <8 x i16>*
+ call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %8, <8 x i16>* %10, i32 2, <8 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 8
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+define void @vmulh_s8_pred(i8* noalias nocapture %d, i8* noalias nocapture readonly %x, i8* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_s8_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: it lt
+; CHECK-NEXT: poplt {r7, pc}
+; CHECK-NEXT: .LBB22_1: @ %vector.ph
+; CHECK-NEXT: add.w r12, r3, #15
+; CHECK-NEXT: mov.w lr, #1
+; CHECK-NEXT: bic r12, r12, #15
+; CHECK-NEXT: sub.w r12, r12, #16
+; CHECK-NEXT: add.w r12, lr, r12, lsr #4
+; CHECK-NEXT: dls lr, r12
+; CHECK-NEXT: .LBB22_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vctp.8 r3
+; CHECK-NEXT: vpstt
+; CHECK-NEXT: vldrbt.u8 q0, [r1], #16
+; CHECK-NEXT: vldrbt.u8 q1, [r2], #16
+; CHECK-NEXT: vmullt.s8 q2, q1, q0
+; CHECK-NEXT: vmullb.s8 q0, q1, q0
+; CHECK-NEXT: subs r3, #16
+; CHECK-NEXT: vshr.u16 q2, q2, #8
+; CHECK-NEXT: vshr.u16 q0, q0, #8
+; CHECK-NEXT: vmovnt.i16 q0, q2
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vstrbt.8 q0, [r0], #16
+; CHECK-NEXT: le lr, .LBB22_2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 15
+ %n.vec = and i32 %n.rnd.up, -16
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i8, i8* %x, i32 %index
+ %1 = bitcast i8* %0 to <16 x i8>*
+ %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %1, i32 1, <16 x i1> %active.lane.mask, <16 x i8> poison)
+ %2 = sext <16 x i8> %wide.masked.load to <16 x i16>
+ %3 = getelementptr inbounds i8, i8* %y, i32 %index
+ %4 = bitcast i8* %3 to <16 x i8>*
+ %wide.masked.load12 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %4, i32 1, <16 x i1> %active.lane.mask, <16 x i8> poison)
+ %5 = sext <16 x i8> %wide.masked.load12 to <16 x i16>
+ %6 = mul nsw <16 x i16> %5, %2
+ %7 = lshr <16 x i16> %6, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %8 = trunc <16 x i16> %7 to <16 x i8>
+ %9 = getelementptr inbounds i8, i8* %d, i32 %index
+ %10 = bitcast i8* %9 to <16 x i8>*
+ call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %8, <16 x i8>* %10, i32 1, <16 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 16
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+define void @vmulh_u8_pred(i8* noalias nocapture %d, i8* noalias nocapture readonly %x, i8* noalias nocapture readonly %y, i32 %n) {
+; CHECK-LABEL: vmulh_u8_pred:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: cmp r3, #1
+; CHECK-NEXT: it lt
+; CHECK-NEXT: poplt {r7, pc}
+; CHECK-NEXT: .LBB23_1: @ %vector.ph
+; CHECK-NEXT: add.w r12, r3, #15
+; CHECK-NEXT: mov.w lr, #1
+; CHECK-NEXT: bic r12, r12, #15
+; CHECK-NEXT: sub.w r12, r12, #16
+; CHECK-NEXT: add.w r12, lr, r12, lsr #4
+; CHECK-NEXT: dls lr, r12
+; CHECK-NEXT: .LBB23_2: @ %vector.body
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vctp.8 r3
+; CHECK-NEXT: vpstt
+; CHECK-NEXT: vldrbt.u8 q0, [r1], #16
+; CHECK-NEXT: vldrbt.u8 q1, [r2], #16
+; CHECK-NEXT: vmullt.u8 q2, q1, q0
+; CHECK-NEXT: vmullb.u8 q0, q1, q0
+; CHECK-NEXT: subs r3, #16
+; CHECK-NEXT: vshr.u16 q2, q2, #8
+; CHECK-NEXT: vshr.u16 q0, q0, #8
+; CHECK-NEXT: vmovnt.i16 q0, q2
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vstrbt.8 q0, [r0], #16
+; CHECK-NEXT: le lr, .LBB23_2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %cmp10 = icmp sgt i32 %n, 0
+ br i1 %cmp10, label %vector.ph, label %for.cond.cleanup
+
+vector.ph: ; preds = %entry
+ %n.rnd.up = add i32 %n, 15
+ %n.vec = and i32 %n.rnd.up, -16
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %n)
+ %0 = getelementptr inbounds i8, i8* %x, i32 %index
+ %1 = bitcast i8* %0 to <16 x i8>*
+ %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %1, i32 1, <16 x i1> %active.lane.mask, <16 x i8> poison)
+ %2 = zext <16 x i8> %wide.masked.load to <16 x i16>
+ %3 = getelementptr inbounds i8, i8* %y, i32 %index
+ %4 = bitcast i8* %3 to <16 x i8>*
+ %wide.masked.load12 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %4, i32 1, <16 x i1> %active.lane.mask, <16 x i8> poison)
+ %5 = zext <16 x i8> %wide.masked.load12 to <16 x i16>
+ %6 = mul nuw <16 x i16> %5, %2
+ %7 = lshr <16 x i16> %6, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %8 = trunc <16 x i16> %7 to <16 x i8>
+ %9 = getelementptr inbounds i8, i8* %d, i32 %index
+ %10 = bitcast i8* %9 to <16 x i8>*
+ call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %8, <16 x i8>* %10, i32 1, <16 x i1> %active.lane.mask)
+ %index.next = add i32 %index, 16
+ %11 = icmp eq i32 %index.next, %n.vec
+ br i1 %11, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup: ; preds = %vector.body, %entry
+ ret void
+}
+
+declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
+declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
+declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
+declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
+declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
+declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
+declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
+declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
+declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
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