[PATCH] D103015: [NFC] Add CHECK lines for unordered FP reductions

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll:131
+; CHECK-UNORDERED: %[[LOAD2:.*]] = load float, float* %[[ARRAYIDX]]
+; CHECK-UNORDERED: vector.ph
+; CHECK-UNORDERED: %[[STEPVEC1:.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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david-arm wrote:
> nit: It looks like none of the variables in the `vector.ph` is actually used further down. Maybe it's possible to just delete the whole `vector.ph` block since it's tested in ORDERED case anyway, unless you're now going to add PHIs to the vector.body which show INDUCTION being used?
These weren't being used, though I've kept them here now that I've added check lines for the PHI nodes that use LOAD1/LOAD2


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  https://reviews.llvm.org/D103015/new/

https://reviews.llvm.org/D103015