[llvm] d70e919 - [RISCV] Optimize getVLENFactoredAmount function.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon May 24 10:06:15 PDT 2021
Author: luxufan
Date: 2021-05-24T10:04:37-07:00
New Revision: d70e9195a3339a6d56ed46ad4b8b467a0053322a
URL: https://github.com/llvm/llvm-project/commit/d70e9195a3339a6d56ed46ad4b8b467a0053322a
DIFF: https://github.com/llvm/llvm-project/commit/d70e9195a3339a6d56ed46ad4b8b467a0053322a.diff
LOG: [RISCV] Optimize getVLENFactoredAmount function.
If the local variable `NumOfVReg` isPowerOf2_32(NumOfVReg - 1) or isPowerOf2_32(NumOfVReg + 1), the ADDI and MUL instructions can be replaced with SLLI and ADD(or SUB) instructions.
Based on original patch by StephenFan.
Reviewed By: frasercrmck, StephenFan
Differential Revision: https://reviews.llvm.org/D100577
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ba99765cd8eae..d6a5ef0dd3d54 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1377,6 +1377,24 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
.addReg(VL, RegState::Kill)
.addImm(ShiftAmount);
+ } else if (isPowerOf2_32(NumOfVReg - 1)) {
+ Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ uint32_t ShiftAmount = Log2_32(NumOfVReg - 1);
+ BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
+ .addReg(VL)
+ .addImm(ShiftAmount);
+ BuildMI(MBB, II, DL, TII->get(RISCV::ADD), VL)
+ .addReg(ScaledRegister, RegState::Kill)
+ .addReg(VL, RegState::Kill);
+ } else if (isPowerOf2_32(NumOfVReg + 1)) {
+ Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
+ BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
+ .addReg(VL)
+ .addReg(ShiftAmount);
+ BuildMI(MBB, II, DL, TII->get(RISCV::SUB), VL)
+ .addReg(ScaledRegister, RegState::Kill)
+ .addReg(VL, RegState::Kill);
} else {
Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N)
diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
index 00642d3f24d5e..187f407ce7986 100644
--- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -77,12 +77,12 @@ define void @lmul1_and_2() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@@ -121,8 +121,8 @@ define void @lmul1_and_4() nounwind {
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 5
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 2
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
@@ -140,12 +140,12 @@ define void @lmul2_and_1() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
@@ -162,8 +162,8 @@ define void @lmul4_and_1() nounwind {
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 5
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 2
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
@@ -252,14 +252,14 @@ define void @gpr_and_lmul1_and_2() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: addi a0, zero, 3
; CHECK-NEXT: sd a0, 24(sp)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
@@ -278,8 +278,8 @@ define void @gpr_and_lmul1_and_4() nounwind {
; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 5
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 2
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi a0, zero, 3
@@ -304,8 +304,8 @@ define void @lmul_1_2_4_8() nounwind {
; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 15
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, vl
+; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -64
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
index b5a7af0cd2f1d..ba7905f9c0f32 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
@@ -9,8 +9,8 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, 15
@@ -22,8 +22,8 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: addi a2, a2, -32
; CHECK-NEXT: vl1re64.v v25, (a2)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub a2, s0, a2
; CHECK-NEXT: addi a2, a2, -32
; CHECK-NEXT: vl2re64.v v26, (a2)
@@ -56,8 +56,8 @@ define void @rvv_overaligned() nounwind {
; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 128
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 1
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: csrr a0, vlenb
@@ -94,8 +94,8 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 128
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 1
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: mv s1, sp
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