[PATCH] D103028: [llvm][ARM] Add CPU defs for arm2/3/6/7m

[David Spickett via Phabricator via llvm-commits]

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These are legacy CPUs that clang knows about but not llvm.

Note that they do not map 1 to 1 for example the "7m"
CPU uses the "v3m" ISA. (also you might think the arm7m
would be armv4 like the arm7tdmi but no it's v3)

Information is thin on the ground for these older chips
so this is the best I found:
https://en.wikichip.org/wiki/acorn/microarchitectures/arm2
https://en.wikichip.org/wiki/acorn/microarchitectures/arm3
https://en.wikichip.org/wiki/arm_holdings/microarchitectures/arm6
https://en.wikichip.org/wiki/arm_holdings/microarchitectures/arm7

You could argue to remove them but since the backend already
knows about the ISA versions it's simple enough to add them.

Previously you could compile with, say, armv3m but you would
get a lot of "unknown processor" warnings along the way.

Final part of fixing https://bugs.llvm.org/show_bug.cgi?id=50454.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103028

Files:
  llvm/lib/Target/ARM/ARM.td
  llvm/test/CodeGen/ARM/pr50454.ll


Index: llvm/test/CodeGen/ARM/pr50454.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/pr50454.ll
@@ -0,0 +1,9 @@
+;; At one point these CPUs were only know to Clang because
+;; they were defined in the Arm target parser but not in ARM.td.
+
+; RUN: llc < %s -mtriple=armv2-unknown-eabi -mcpu=arm2 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv2a-unknown-eabi -mcpu=arm3 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv3-unknown-eabi -mcpu=arm6 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv3m-unknown-eabi -mcpu=arm7m 2>&1 | FileCheck %s
+
+; CHECK-NOT: {{.*}} is not a recognized processor for this target (ignoring processor)
Index: llvm/lib/Target/ARM/ARM.td
===================================================================
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -963,6 +963,11 @@
 // FIXME: Several processors below are not using their own scheduler
 // model, but one of similar/previous processor. These should be fixed.
 
+def : ProcNoItin<"arm2",                                [ARMv2]>;
+def : ProcNoItin<"arm3",                                [ARMv2a]>;
+def : ProcNoItin<"arm6",                                [ARMv3]>;
+def : ProcNoItin<"arm7m",                               [ARMv3m]>;
+
 def : ProcNoItin<"arm8",                                [ARMv4]>;
 def : ProcNoItin<"arm810",                              [ARMv4]>;
 def : ProcNoItin<"strongarm",                           [ARMv4]>;


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