[PATCH] D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 24 03:31:46 PDT 2021

Previous message: [llvm] 53c42f7 - [ARM] Ensure WLS preheader blocks have branches during memcpy lowering
Next message: [PATCH] D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

dmgreen added a comment.

Sounds good. Can we make sure there is test coverage for big endian too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102938/new/

https://reviews.llvm.org/D102938

Previous message: [llvm] 53c42f7 - [ARM] Ensure WLS preheader blocks have branches during memcpy lowering
Next message: [PATCH] D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list