[PATCH] D102777: [AArch64][SVE] Add fixed length codegen for FP_TO_{S,U}INT/{S,U}INT_TO_FP

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm accepted this revision.
peterwaller-arm added a comment.
This revision is now accepted and ready to land.

LGTM. Optional nit.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18060
+  unsigned Opcode = IsSigned ? AArch64ISD::FCVTZS_MERGE_PASSTHRU
+                             : AArch64ISD::FCVTZU_MERGE_PASSTHRU;
+
----------------
Nit: suggestion: a name like 'CvtOpcode' would be a small readability improvement in use at DAG.getNode().


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102777/new/

https://reviews.llvm.org/D102777