[PATCH] D95322: [RISCV] Custom type legalize i8/i16 UDIV/UREM/SDIV on RV64 so we can use divuw/remuw/divw.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2201
+    break;
+  }
   case RISCVISD::READ_VLENB:
----------------
Jim wrote:
> I met a bug that removes a and mask.
> ```
> typedef unsigned char uint8x2_t __attribute__((vector_size(2)));
> 
> uint8x2_t udiv(uint8x2_t *a, uint8x2_t *b) {
>   return *a / *b;
> }
> ```
> 
> Assembly look like:
> divu    a1, a3, a1
> divu    a0, a0, a2 
> slli       a1, a1, 8
> or        a0, a0, a1 >> missing "and a0, a0, 256" before or operation
> 
> If element 0 of *b is zero, it a division by zero. a0 would be 0xffffffff. 
> So the result of or operation is incorrect. 
> Is it a undefined behavior?
> For vectors, if any element of the divisor is zero, the operation has undefined behavior.

>From LangRef.


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  https://reviews.llvm.org/D95322/new/

https://reviews.llvm.org/D95322