[PATCH] D102505: [RISCV] Support vector types in combination with fastcc

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7160
+    if (unsigned Reg =
+            allocateRVVReg(ValVT, ValNo, FirstMaskArgument, State, TLI)) {
+      // Fixed-length vectors are located in the corresponding scalable-vector
----------------
Should we allow all the vector registers used to pass vector arguments under fastcc, instead of limiting to v8 to v23?


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  https://reviews.llvm.org/D102505/new/

https://reviews.llvm.org/D102505