[PATCH] D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
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Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
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The existing LD1 patterns do not cover cases where result type does
not match the memory type. This happens when illegal vector types are
extended and scalarized, for example:

  load <2 x i16>* %v2i16

is lowered into:

  // first element
  (v4i32 (insert_subvector (v2i32 (scalar_to_vector (load anyext from i16)))))
  // other elements
  (v4i32 (insert_vector_elt (i32 (load anyext from i16)) idx))

Before this patch these patterns were compiled into LDR + INS.
Now they are compiled into LD1.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102938

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

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