[PATCH] D102870: [RFC] [WIP] CodeGen: Print/parse LLTs in MachineMemOperands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, paquette, dsanders, qcolombet, bogner, RKSimon, thegameg, craig.topper.
Herald added subscribers: kerbowa, jfb, hiraditya, nhaehnle, jvesely.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

      

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.


https://reviews.llvm.org/D102870

Files:
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
  llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
  llvm/test/CodeGen/MIR/AArch64/base-memoperands.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
  llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
  llvm/test/CodeGen/MIR/AArch64/swp.mir
  llvm/test/CodeGen/MIR/AArch64/target-memoperands.mir
  llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll