[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Luke via Phabricator via llvm-commits]

luke957 added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:6
+; CHECK: LV: IC is 2
+; CHECK: %{{.*}} = add {{.*}}, 8
+
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craig.topper wrote:
> Is this just checking the induction variable increment? I'd really like to see what vector instructions it generates.
For this test case, vf and uf will be 4 and 2 respectively. So the vector instructions will repeat once in one trip, and there will be an instruction like `%{{.*}} = add <4 x i32> %{{.*}}, <i32 4, i32 4, i32 4, i32 4>`.


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  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469