[PATCH] D102605: [CodeGen] Add support for widening the result of EXTRACT_SUBVECTOR
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 20 04:27:27 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa21bff0673a1: [CodeGen] Add support for widening the result of EXTRACT_SUBVECTOR (authored by david-arm).
Changed prior to commit:
https://reviews.llvm.org/D102605?vs=345811&id=346699#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102605/new/
https://reviews.llvm.org/D102605
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/AArch64/sve-extract-vector.ll
llvm/test/CodeGen/AArch64/sve-int-arith.ll
Index: llvm/test/CodeGen/AArch64/sve-int-arith.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-int-arith.ll
+++ llvm/test/CodeGen/AArch64/sve-int-arith.ll
@@ -45,6 +45,16 @@
ret <vscale x 16 x i8> %res
}
+define <vscale x 1 x i32> @add_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
+; CHECK-LABEL: add_nxv1i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = add <vscale x 1 x i32> %a, %b
+ ret <vscale x 1 x i32> %c
+}
+
define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: sub_i64:
; CHECK: // %bb.0:
Index: llvm/test/CodeGen/AArch64/sve-extract-vector.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-extract-vector.ll
+++ llvm/test/CodeGen/AArch64/sve-extract-vector.ll
@@ -105,7 +105,30 @@
ret <16 x i8> %retval
}
+
+; Extracting illegal subvectors
+
+define <vscale x 1 x i32> @extract_nxv1i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
+; CHECK-LABEL: extract_nxv1i32_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
+ %retval = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
+ ret <vscale x 1 x i32> %retval
+}
+
+define <vscale x 1 x i16> @extract_nxv1i16_nxv6i16(<vscale x 6 x i16> %vec) nounwind {
+; CHECK-LABEL: extract_nxv1i16_nxv6i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
+ %retval = call <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16> %vec, i64 0)
+ ret <vscale x 1 x i16> %retval
+}
+
+
declare <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64)
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
+
+declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32>, i64)
+declare <vscale x 1 x i16> @llvm.experimental.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16>, i64)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3960,7 +3960,6 @@
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
EVT VT = N->getValueType(0);
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
SDValue Idx = N->getOperand(1);
SDLoc dl(N);
@@ -3975,7 +3974,12 @@
if (IdxVal == 0 && InVT == WidenVT)
return InOp;
+ if (VT.isScalableVector())
+ report_fatal_error("Don't know how to widen the result of "
+ "EXTRACT_SUBVECTOR for scalable vectors");
+
// Check if we can extract from the vector.
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();
unsigned InNumElts = InVT.getVectorNumElements();
if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
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