[PATCH] D102766: [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll:108
+  %subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
+  %ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2)
+  ret <vscale x 4 x i16> %ins
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As I understand it, this should overwrite elements with indices {2,3} of %vec, but this seems to overwrite elements {1,2}. So I am not convinced this is correct.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102766/new/

https://reviews.llvm.org/D102766