[llvm] 0f88328 - [AArch64] Add extra codegen tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu May 20 03:33:02 PDT 2021
Author: David Green
Date: 2021-05-20T11:32:51+01:00
New Revision: 0f88328867f4a309a558d1064e2cbb936e240629
URL: https://github.com/llvm/llvm-project/commit/0f88328867f4a309a558d1064e2cbb936e240629
DIFF: https://github.com/llvm/llvm-project/commit/0f88328867f4a309a558d1064e2cbb936e240629.diff
LOG: [AArch64] Add extra codegen tests. NFC
This adds some extra codegen tests for abs and hadd, regenerating some
of the existing tests with updated check lines.
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-vabs.ll
llvm/test/CodeGen/AArch64/arm64-vhadd.ll
llvm/test/CodeGen/AArch64/neg-abs.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index f2ba768af1dc..a5945bb7ac76 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,79 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,DAG %s
-; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=FALLBACK,CHECK,GISEL
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL,FALLBACK
; FALLBACK-NOT: remark:{{.*}} sabdl8h
define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sabdl8h:
-;CHECK: sabdl.8h
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
+; CHECK-LABEL: sabdl8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabdl.8h v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
}
; FALLBACK-NOT: remark:{{.*}} sabdl4s
define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sabdl4s:
-;CHECK: sabdl.4s
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
+; CHECK-LABEL: sabdl4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabdl.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
}
; FALLBACK-NOT: remark:{{.*}} sabdl2d
define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sabdl2d:
-;CHECK: sabdl.2d
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
+; CHECK-LABEL: sabdl2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
}
define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sabdl2_8h:
-;CHECK: sabdl.8h
- %load1 = load <16 x i8>, <16 x i8>* %A
- %load2 = load <16 x i8>, <16 x i8>* %B
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
+; CHECK-LABEL: sabdl2_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: sabdl.8h v0, v0, v1
+; CHECK-NEXT: ret
+ %load1 = load <16 x i8>, <16 x i8>* %A
+ %load2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
}
define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sabdl2_4s:
-;CHECK: sabdl.4s
- %load1 = load <8 x i16>, <8 x i16>* %A
- %load2 = load <8 x i16>, <8 x i16>* %B
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
+; CHECK-LABEL: sabdl2_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: sabdl.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %load1 = load <8 x i16>, <8 x i16>* %A
+ %load2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
}
define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sabdl2_2d:
-;CHECK: sabdl.2d
- %load1 = load <4 x i32>, <4 x i32>* %A
- %load2 = load <4 x i32>, <4 x i32>* %B
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
+; CHECK-LABEL: sabdl2_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: sabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
+ %load1 = load <4 x i32>, <4 x i32>* %A
+ %load2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
+ ret <2 x i64> %tmp4
}
; FALLBACK-NOT: remark:{{.*}} uabdl8h)
define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uabdl8h:
-;CHECK: uabdl.8h
+; CHECK-LABEL: uabdl8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabdl.8h v0, v0, v1
+; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -83,8 +112,12 @@ define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; FALLBACK-NOT: remark:{{.*}} uabdl4s)
define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uabdl4s:
-;CHECK: uabdl.4s
+; CHECK-LABEL: uabdl4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabdl.4s v0, v0, v1
+; CHECK-NEXT: ret
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -94,8 +127,12 @@ define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; FALLBACK-NOT: remark:{{.*}} uabdl2d)
define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uabdl2d:
-;CHECK: uabdl.2d
+; CHECK-LABEL: uabdl2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -104,8 +141,12 @@ define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uabdl2_8h:
-;CHECK: uabdl.8h
+; CHECK-LABEL: uabdl2_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: uabdl.8h v0, v0, v1
+; CHECK-NEXT: ret
%load1 = load <16 x i8>, <16 x i8>* %A
%load2 = load <16 x i8>, <16 x i8>* %B
%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -117,8 +158,12 @@ define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uabdl2_4s:
-;CHECK: uabdl.4s
+; CHECK-LABEL: uabdl2_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: uabdl.4s v0, v0, v1
+; CHECK-NEXT: ret
%load1 = load <8 x i16>, <8 x i16>* %A
%load2 = load <8 x i16>, <8 x i16>* %B
%tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -129,8 +174,12 @@ define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uabdl2_2d:
-;CHECK: uabdl.2d
+; CHECK-LABEL: uabdl2_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0, #8]
+; CHECK-NEXT: ldr d1, [x1, #8]
+; CHECK-NEXT: uabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
%load1 = load <4 x i32>, <4 x i32>* %A
%load2 = load <4 x i32>, <4 x i32>* %B
%tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -144,8 +193,16 @@ declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
define i16 @uabd16b_rdx(<16 x i8>* %a, <16 x i8>* %b) {
-; CHECK-LABEL: uabd16b_rdx
-; CHECK: uabd.16b
+; CHECK-LABEL: uabd16b_rdx:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.16b v0, v0, v1
+; CHECK-NEXT: ushll.8h v1, v0, #0
+; CHECK-NEXT: uaddw2.8h v0, v1, v0
+; CHECK-NEXT: addv.8h h0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%aload = load <16 x i8>, <16 x i8>* %a, align 1
%bload = load <16 x i8>, <16 x i8>* %b, align 1
%aext = zext <16 x i8> %aload to <16 x i16>
@@ -159,8 +216,17 @@ define i16 @uabd16b_rdx(<16 x i8>* %a, <16 x i8>* %b) {
}
define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: uabd16b_rdx_i32
-; CHECK: uabd.16b
+; CHECK-LABEL: uabd16b_rdx_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uabd.16b v0, v0, v1
+; CHECK-NEXT: ushll2.8h v1, v0, #0
+; CHECK-NEXT: ushll.8h v0, v0, #0
+; CHECK-NEXT: uaddl2.4s v2, v0, v1
+; CHECK-NEXT: uaddl.4s v0, v0, v1
+; CHECK-NEXT: add.4s v0, v0, v2
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%aext = zext <16 x i8> %a to <16 x i32>
%bext = zext <16 x i8> %b to <16 x i32>
%ab
diff = sub nsw <16 x i32> %aext, %bext
@@ -172,8 +238,17 @@ define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
}
define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: sabd16b_rdx_i32
-; CHECK: sabd.16b
+; CHECK-LABEL: sabd16b_rdx_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sabd.16b v0, v0, v1
+; CHECK-NEXT: ushll2.8h v1, v0, #0
+; CHECK-NEXT: ushll.8h v0, v0, #0
+; CHECK-NEXT: uaddl2.4s v2, v0, v1
+; CHECK-NEXT: uaddl.4s v0, v0, v1
+; CHECK-NEXT: add.4s v0, v0, v2
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%aext = sext <16 x i8> %a to <16 x i32>
%bext = sext <16 x i8> %b to <16 x i32>
%ab
diff = sub nsw <16 x i32> %aext, %bext
@@ -189,8 +264,16 @@ declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
define i32 @uabd8h_rdx(<8 x i16>* %a, <8 x i16>* %b) {
-; CHECK-LABEL: uabd8h_rdx
-; CHECK: uabd.8h
+; CHECK-LABEL: uabd8h_rdx:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.8h v0, v0, v1
+; CHECK-NEXT: ushll.4s v1, v0, #0
+; CHECK-NEXT: uaddw2.4s v0, v1, v0
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%aload = load <8 x i16>, <8 x i16>* %a, align 1
%bload = load <8 x i16>, <8 x i16>* %b, align 1
%aext = zext <8 x i16> %aload to <8 x i32>
@@ -204,8 +287,14 @@ define i32 @uabd8h_rdx(<8 x i16>* %a, <8 x i16>* %b) {
}
define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-LABEL: sabd8h_rdx
-; CHECK: sabd.8h
+; CHECK-LABEL: sabd8h_rdx:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sabd.8h v0, v0, v1
+; CHECK-NEXT: ushll.4s v1, v0, #0
+; CHECK-NEXT: uaddw2.4s v0, v1, v0
+; CHECK-NEXT: addv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%aext = sext <8 x i16> %a to <8 x i32>
%bext = sext <8 x i16> %b to <8 x i32>
%ab
diff = sub nsw <8 x i32> %aext, %bext
@@ -217,11 +306,27 @@ define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
}
define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: uabdl4s_rdx_i32
-; DAG: uabdl.4s
+; DAG-LABEL: uabdl4s_rdx_i32:
+; DAG: // %bb.0:
+; DAG-NEXT: uabdl.4s v0, v0, v1
+; DAG-NEXT: addv.4s s0, v0
+; DAG-NEXT: fmov w0, s0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: uabdl4s_rdx_i32:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v2, #0000000000000000
+; GISEL-NEXT: usubl.4s v0, v0, v1
+; GISEL-NEXT: cmgt.4s v1, v2, v0
+; GISEL-NEXT: shl.4s v1, v1, #31
+; GISEL-NEXT: neg.4s v2, v0
+; GISEL-NEXT: sshr.4s v1, v1, #31
+; GISEL-NEXT: bit.16b v0, v2, v1
+; GISEL-NEXT: addv.4s s0, v0
+; GISEL-NEXT: fmov w0, s0
+; GISEL-NEXT: ret
; GISel doesn't match this pattern yet.
-; GISEL: addv.4s
%aext = zext <4 x i16> %a to <4 x i32>
%bext = zext <4 x i16> %b to <4 x i32>
%ab
diff = sub nsw <4 x i32> %aext, %bext
@@ -236,8 +341,16 @@ declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
define i64 @uabd4s_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
-; CHECK: uabd4s_rdx
-; CHECK: uabd.4s
+; CHECK-LABEL: uabd4s_rdx:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.4s v0, v0, v1
+; CHECK-NEXT: ushll.2d v1, v0, #0
+; CHECK-NEXT: uaddw2.2d v0, v1, v0
+; CHECK-NEXT: addp.2d d0, v0
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%aload = load <4 x i32>, <4 x i32>* %a, align 1
%bload = load <4 x i32>, <4 x i32>* %b, align 1
%aext = zext <4 x i32> %aload to <4 x i64>
@@ -251,8 +364,14 @@ define i64 @uabd4s_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
}
define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
-; CHECK: sabd4s_rdx
-; CHECK: sabd.4s
+; CHECK-LABEL: sabd4s_rdx:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sabd.4s v0, v0, v1
+; CHECK-NEXT: ushll.2d v1, v0, #0
+; CHECK-NEXT: uaddw2.2d v0, v1, v0
+; CHECK-NEXT: addp.2d d0, v0
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%aext = sext <4 x i32> %a to <4 x i64>
%bext = sext <4 x i32> %b to <4 x i64>
%ab
diff = sub nsw <4 x i64> %aext, %bext
@@ -264,11 +383,27 @@ define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
}
define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: uabdl2d_rdx_i64
-; DAG: uabdl.2d
+; DAG-LABEL: uabdl2d_rdx_i64:
+; DAG: // %bb.0:
+; DAG-NEXT: uabdl.2d v0, v0, v1
+; DAG-NEXT: addp.2d d0, v0
+; DAG-NEXT: fmov x0, d0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: uabdl2d_rdx_i64:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v2, #0000000000000000
+; GISEL-NEXT: usubl.2d v0, v0, v1
+; GISEL-NEXT: cmgt.2d v1, v2, v0
+; GISEL-NEXT: shl.2d v1, v1, #63
+; GISEL-NEXT: neg.2d v2, v0
+; GISEL-NEXT: sshr.2d v1, v1, #63
+; GISEL-NEXT: bit.16b v0, v2, v1
+; GISEL-NEXT: addp.2d d0, v0
+; GISEL-NEXT: fmov x0, d0
+; GISEL-NEXT: ret
; GISel doesn't match this pattern yet
-; GISEL: addp.2d
%aext = zext <2 x i32> %a to <2 x i64>
%bext = zext <2 x i32> %b to <2 x i64>
%ab
diff = sub nsw <2 x i64> %aext, %bext
@@ -280,30 +415,42 @@ define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
}
define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_2s:
-;CHECK: fabd.2s
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
+; CHECK-LABEL: fabd_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: fabd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
}
define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_4s:
-;CHECK: fabd.4s
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
+; CHECK-LABEL: fabd_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: fabd.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
}
define <2 x double> @fabd_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fabd_2d:
-;CHECK: fabd.2d
- %tmp1 = load <2 x double>, <2 x double>* %A
- %tmp2 = load <2 x double>, <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
+; CHECK-LABEL: fabd_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: fabd.2d v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x double>, <2 x double>* %A
+ %tmp2 = load <2 x double>, <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
}
declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone
@@ -311,33 +458,45 @@ declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>) noun
declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone
define <2 x float> @fabd_2s_from_fsub_fabs(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_2s_from_fsub_fabs:
-;CHECK: fabd.2s
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
- %sub = fsub <2 x float> %tmp1, %tmp2
- %abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %sub)
- ret <2 x float> %abs
+; CHECK-LABEL: fabd_2s_from_fsub_fabs:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: fabd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp2 = load <2 x float>, <2 x float>* %B
+ %sub = fsub <2 x float> %tmp1, %tmp2
+ %abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %sub)
+ ret <2 x float> %abs
}
define <4 x float> @fabd_4s_from_fsub_fabs(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_4s_from_fsub_fabs:
-;CHECK: fabd.4s
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
- %sub = fsub <4 x float> %tmp1, %tmp2
- %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %sub)
- ret <4 x float> %abs
+; CHECK-LABEL: fabd_4s_from_fsub_fabs:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: fabd.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp2 = load <4 x float>, <4 x float>* %B
+ %sub = fsub <4 x float> %tmp1, %tmp2
+ %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %sub)
+ ret <4 x float> %abs
}
define <2 x double> @fabd_2d_from_fsub_fabs(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fabd_2d_from_fsub_fabs:
-;CHECK: fabd.2d
- %tmp1 = load <2 x double>, <2 x double>* %A
- %tmp2 = load <2 x double>, <2 x double>* %B
- %sub = fsub <2 x double> %tmp1, %tmp2
- %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %sub)
- ret <2 x double> %abs
+; CHECK-LABEL: fabd_2d_from_fsub_fabs:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: fabd.2d v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x double>, <2 x double>* %A
+ %tmp2 = load <2 x double>, <2 x double>* %B
+ %sub = fsub <2 x double> %tmp1, %tmp2
+ %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %sub)
+ ret <2 x double> %abs
}
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone
@@ -345,57 +504,81 @@ declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sabd_8b:
-;CHECK: sabd.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
+; CHECK-LABEL: sabd_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabd.8b v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
}
define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sabd_16b:
-;CHECK: sabd.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
+; CHECK-LABEL: sabd_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: sabd.16b v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
}
define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sabd_4h:
-;CHECK: sabd.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
+; CHECK-LABEL: sabd_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabd.4h v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
}
define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sabd_8h:
-;CHECK: sabd.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
+; CHECK-LABEL: sabd_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: sabd.8h v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
}
define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sabd_2s:
-;CHECK: sabd.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
+; CHECK-LABEL: sabd_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sabd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
}
define <4 x i32> @sabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sabd_4s:
-;CHECK: sabd.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
+; CHECK-LABEL: sabd_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: sabd.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
}
declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
@@ -406,57 +589,81 @@ declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>) nounwind r
declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uabd_8b:
-;CHECK: uabd.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
+; CHECK-LABEL: uabd_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabd.8b v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
}
define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uabd_16b:
-;CHECK: uabd.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
+; CHECK-LABEL: uabd_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.16b v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
}
define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uabd_4h:
-;CHECK: uabd.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
+; CHECK-LABEL: uabd_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabd.4h v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
}
define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uabd_8h:
-;CHECK: uabd.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
+; CHECK-LABEL: uabd_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.8h v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
}
define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uabd_2s:
-;CHECK: uabd.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
+; CHECK-LABEL: uabd_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uabd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
}
define <4 x i32> @uabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uabd_4s:
-;CHECK: uabd.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
+; CHECK-LABEL: uabd_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ldr q1, [x1]
+; CHECK-NEXT: uabd.4s v0, v0, v1
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
}
declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
@@ -467,51 +674,69 @@ declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>) nounwind r
declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqabs_8b:
-;CHECK: sqabs.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
+; CHECK-LABEL: sqabs_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqabs.8b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp3
}
define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqabs_16b:
-;CHECK: sqabs.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
+; CHECK-LABEL: sqabs_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqabs.16b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp3
}
define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqabs_4h:
-;CHECK: sqabs.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
+; CHECK-LABEL: sqabs_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqabs.4h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp3
}
define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqabs_8h:
-;CHECK: sqabs.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
+; CHECK-LABEL: sqabs_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqabs.8h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp3
}
define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqabs_2s:
-;CHECK: sqabs.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
+; CHECK-LABEL: sqabs_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqabs.2s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp3
}
define <4 x i32> @sqabs_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqabs_4s:
-;CHECK: sqabs.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
+; CHECK-LABEL: sqabs_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqabs.4s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp3
}
declare <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8>) nounwind readnone
@@ -522,51 +747,69 @@ declare <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone
define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqneg_8b:
-;CHECK: sqneg.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
+; CHECK-LABEL: sqneg_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqneg.8b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp3
}
define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqneg_16b:
-;CHECK: sqneg.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
+; CHECK-LABEL: sqneg_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqneg.16b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp3
}
define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqneg_4h:
-;CHECK: sqneg.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
+; CHECK-LABEL: sqneg_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqneg.4h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp3
}
define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqneg_8h:
-;CHECK: sqneg.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
+; CHECK-LABEL: sqneg_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqneg.8h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp3
}
define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqneg_2s:
-;CHECK: sqneg.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
+; CHECK-LABEL: sqneg_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: sqneg.2s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp3
}
define <4 x i32> @sqneg_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqneg_4s:
-;CHECK: sqneg.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
+; CHECK-LABEL: sqneg_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: sqneg.4s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp3
}
declare <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8>) nounwind readnone
@@ -577,63 +820,87 @@ declare <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone
define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: abs_8b:
-;CHECK: abs.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
+; CHECK-LABEL: abs_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: abs.8b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp3
}
define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: abs_16b:
-;CHECK: abs.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
+; CHECK-LABEL: abs_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: abs.16b v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp3
}
define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: abs_4h:
-;CHECK: abs.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
+; CHECK-LABEL: abs_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: abs.4h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp3
}
define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: abs_8h:
-;CHECK: abs.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
+; CHECK-LABEL: abs_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: abs.8h v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp3
}
define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: abs_2s:
-;CHECK: abs.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
+; CHECK-LABEL: abs_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: abs.2s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp3
}
define <4 x i32> @abs_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: abs_4s:
-;CHECK: abs.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
+; CHECK-LABEL: abs_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: abs.4s v0, v0
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp3
}
define <1 x i64> @abs_1d(<1 x i64> %A) nounwind {
; CHECK-LABEL: abs_1d:
-; CHECK: abs d0, d0
+; CHECK: // %bb.0:
+; CHECK-NEXT: abs d0, d0
+; CHECK-NEXT: ret
%abs = call <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64> %A)
ret <1 x i64> %abs
}
define i64 @abs_1d_honestly(i64 %A) nounwind {
; CHECK-LABEL: abs_1d_honestly:
-; CHECK: abs d0, d0
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: abs d0, d0
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%abs = call i64 @llvm.aarch64.neon.abs.i64(i64 %A)
ret i64 %abs
}
@@ -649,310 +916,434 @@ declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone
; FALLBACK-NOT: remark:{{.*}} sabal8h
define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: sabal8h:
-;CHECK: sabal.8h
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
+; CHECK-LABEL: sabal8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: sabal.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4.1
+ ret <8 x i16> %tmp5
}
; FALLBACK-NOT: remark:{{.*}} sabal4s
define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sabal4s:
-;CHECK: sabal.4s
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
+; CHECK-LABEL: sabal4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: sabal.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4.1
+ ret <4 x i32> %tmp5
}
; FALLBACK-NOT: remark:{{.*}} sabal2d
define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sabal2d:
-;CHECK: sabal.2d
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
- %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
+; CHECK-LABEL: sabal2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: sabal.2d v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
+ %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4.1
+ ret <2 x i64> %tmp5
}
define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: sabal2_8h:
-;CHECK: sabal.8h
- %load1 = load <16 x i8>, <16 x i8>* %A
- %load2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
+; CHECK-LABEL: sabal2_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: sabal.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <16 x i8>, <16 x i8>* %A
+ %load2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4.1
+ ret <8 x i16> %tmp5
}
define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sabal2_4s:
-;CHECK: sabal.4s
- %load1 = load <8 x i16>, <8 x i16>* %A
- %load2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
+; CHECK-LABEL: sabal2_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: sabal.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <8 x i16>, <8 x i16>* %A
+ %load2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4.1
+ ret <4 x i32> %tmp5
}
define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sabal2_2d:
-;CHECK: sabal.2d
- %load1 = load <4 x i32>, <4 x i32>* %A
- %load2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
+; CHECK-LABEL: sabal2_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: sabal.2d v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <4 x i32>, <4 x i32>* %A
+ %load2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4.1
+ ret <2 x i64> %tmp5
}
; FALLBACK-NOT: remark:{{.*}} uabal8h
define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uabal8h:
-;CHECK: uabal.8h
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
+; CHECK-LABEL: uabal8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uabal.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4.1
+ ret <8 x i16> %tmp5
}
; FALLBACK-NOT: remark:{{.*}} uabal8s
define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uabal4s:
-;CHECK: uabal.4s
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
+; CHECK-LABEL: uabal4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uabal.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4.1
+ ret <4 x i32> %tmp5
}
; FALLBACK-NOT: remark:{{.*}} uabal2d
define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: uabal2d:
-;CHECK: uabal.2d
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
- %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
+; CHECK-LABEL: uabal2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uabal.2d v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4.1
+ ret <2 x i64> %tmp5
}
define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uabal2_8h:
-;CHECK: uabal.8h
- %load1 = load <16 x i8>, <16 x i8>* %A
- %load2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
+; CHECK-LABEL: uabal2_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: uabal.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <16 x i8>, <16 x i8>* %A
+ %load2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4.1
+ ret <8 x i16> %tmp5
}
define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uabal2_4s:
-;CHECK: uabal.4s
- %load1 = load <8 x i16>, <8 x i16>* %A
- %load2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
+; CHECK-LABEL: uabal2_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: uabal.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <8 x i16>, <8 x i16>* %A
+ %load2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4.1
+ ret <4 x i32> %tmp5
}
define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: uabal2_2d:
-;CHECK: uabal.2d
- %load1 = load <4 x i32>, <4 x i32>* %A
- %load2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
+; CHECK-LABEL: uabal2_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: ldr d1, [x0, #8]
+; CHECK-NEXT: ldr d2, [x1, #8]
+; CHECK-NEXT: uabal.2d v0, v1, v2
+; CHECK-NEXT: ret
+ %load1 = load <4 x i32>, <4 x i32>* %A
+ %load2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
+ %tmp5 = add <2 x i64> %tmp3, %tmp4.1
+ ret <2 x i64> %tmp5
}
define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: saba_8b:
-;CHECK: saba.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = load <8 x i8>, <8 x i8>* %C
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
+; CHECK-LABEL: saba_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: saba.8b v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4 = load <8 x i8>, <8 x i8>* %C
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
}
define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK-LABEL: saba_16b:
-;CHECK: saba.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- %tmp4 = load <16 x i8>, <16 x i8>* %C
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
+; CHECK-LABEL: saba_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: saba.16b v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ %tmp4 = load <16 x i8>, <16 x i8>* %C
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
}
define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: saba_4h:
-;CHECK: saba.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = load <4 x i16>, <4 x i16>* %C
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
+; CHECK-LABEL: saba_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: saba.4h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4 = load <4 x i16>, <4 x i16>* %C
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
}
define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: saba_8h:
-;CHECK: saba.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- %tmp4 = load <8 x i16>, <8 x i16>* %C
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
+; CHECK-LABEL: saba_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: saba.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ %tmp4 = load <8 x i16>, <8 x i16>* %C
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
}
define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: saba_2s:
-;CHECK: saba.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = load <2 x i32>, <2 x i32>* %C
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
+; CHECK-LABEL: saba_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: saba.2s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4 = load <2 x i32>, <2 x i32>* %C
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
}
define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: saba_4s:
-;CHECK: saba.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- %tmp4 = load <4 x i32>, <4 x i32>* %C
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
+; CHECK-LABEL: saba_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: saba.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ %tmp4 = load <4 x i32>, <4 x i32>* %C
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
}
define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: uaba_8b:
-;CHECK: uaba.8b
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = load <8 x i8>, <8 x i8>* %C
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
+; CHECK-LABEL: uaba_8b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: uaba.8b v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ %tmp4 = load <8 x i8>, <8 x i8>* %C
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
}
define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK-LABEL: uaba_16b:
-;CHECK: uaba.16b
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- %tmp4 = load <16 x i8>, <16 x i8>* %C
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
+; CHECK-LABEL: uaba_16b:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uaba.16b v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ %tmp4 = load <16 x i8>, <16 x i8>* %C
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
}
define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: uaba_4h:
-;CHECK: uaba.4h
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = load <4 x i16>, <4 x i16>* %C
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
+; CHECK-LABEL: uaba_4h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: uaba.4h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp4 = load <4 x i16>, <4 x i16>* %C
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
}
define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uaba_8h:
-;CHECK: uaba.8h
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- %tmp4 = load <8 x i16>, <8 x i16>* %C
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
+; CHECK-LABEL: uaba_8h:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uaba.8h v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ %tmp4 = load <8 x i16>, <8 x i16>* %C
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
}
define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: uaba_2s:
-;CHECK: uaba.2s
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = load <2 x i32>, <2 x i32>* %C
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
+; CHECK-LABEL: uaba_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ldr d2, [x1]
+; CHECK-NEXT: ldr d0, [x2]
+; CHECK-NEXT: uaba.2s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp4 = load <2 x i32>, <2 x i32>* %C
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
}
define <4 x i32> @uaba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uaba_4s:
-;CHECK: uaba.4s
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- %tmp4 = load <4 x i32>, <4 x i32>* %C
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
+; CHECK-LABEL: uaba_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: ldr q2, [x1]
+; CHECK-NEXT: ldr q0, [x2]
+; CHECK-NEXT: uaba.4s v0, v1, v2
+; CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ %tmp4 = load <4 x i32>, <4 x i32>* %C
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
}
; Scalar FABD
define float @fabds(float %a, float %b) nounwind {
; CHECK-LABEL: fabds:
-; CHECK: fabd s0, s0, s1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabd s0, s0, s1
+; CHECK-NEXT: ret
%vabd.i = tail call float @llvm.aarch64.sisd.fabd.f32(float %a, float %b) nounwind
ret float %vabd.i
}
define double @fabdd(double %a, double %b) nounwind {
; CHECK-LABEL: fabdd:
-; CHECK: fabd d0, d0, d1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabd d0, d0, d1
+; CHECK-NEXT: ret
%vabd.i = tail call double @llvm.aarch64.sisd.fabd.f64(double %a, double %b) nounwind
ret double %vabd.i
}
@@ -962,7 +1353,9 @@ declare float @llvm.aarch64.sisd.fabd.f32(float, float) nounwind readnone
define float @fabds_from_fsub_fabs(float %a, float %b) nounwind {
; CHECK-LABEL: fabds_from_fsub_fabs:
-; CHECK: fabd s0, s0, s1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabd s0, s0, s1
+; CHECK-NEXT: ret
%sub = fsub float %a, %b
%abs = tail call float @llvm.fabs.f32(float %sub)
ret float %abs
@@ -970,7 +1363,9 @@ define float @fabds_from_fsub_fabs(float %a, float %b) nounwind {
define double @fabdd_from_fsub_fabs(double %a, double %b) nounwind {
; CHECK-LABEL: fabdd_from_fsub_fabs:
-; CHECK: fabd d0, d0, d1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabd d0, d0, d1
+; CHECK-NEXT: ret
%sub = fsub double %a, %b
%abs = tail call double @llvm.fabs.f64(double %sub)
ret double %abs
@@ -981,8 +1376,10 @@ declare double @llvm.fabs.f64(double) nounwind readnone
define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: uabdl_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: uabdl.2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup.2s v1, w0
+; CHECK-NEXT: uabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
@@ -995,8 +1392,10 @@ define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: uabdl2_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: uabdl2.2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup.4s v1, w0
+; CHECK-NEXT: uabdl2.2d v0, v0, v1
+; CHECK-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
@@ -1009,8 +1408,10 @@ define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: sabdl_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: sabdl.2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup.2s v1, w0
+; CHECK-NEXT: sabdl.2d v0, v0, v1
+; CHECK-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
@@ -1023,8 +1424,10 @@ define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: sabdl2_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: sabdl2.2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup.4s v1, w0
+; CHECK-NEXT: sabdl2.2d v0, v0, v1
+; CHECK-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
@@ -1036,98 +1439,220 @@ define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
}
define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
-; CHECK-LABEL: abspattern1:
-; DAG: abs.2s
-; DAG-NEXT: ret
-
-; GISEL-DAG: neg.2s
-; GISEL-DAG: cmge.2s
-; GISEL: bif.8b
- %tmp1neg = sub <2 x i32> zeroinitializer, %a
- %b = icmp sge <2 x i32> %a, zeroinitializer
- %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
- ret <2 x i32> %abs
+; DAG-LABEL: abspattern1:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.2s v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern1:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmge.2s v1, v0, v1
+; GISEL-NEXT: shl.2s v1, v1, #31
+; GISEL-NEXT: neg.2s v2, v0
+; GISEL-NEXT: sshr.2s v1, v1, #31
+; GISEL-NEXT: bif.8b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <2 x i32> zeroinitializer, %a
+ %b = icmp sge <2 x i32> %a, zeroinitializer
+ %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
+ ret <2 x i32> %abs
}
define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
-; CHECK-LABEL: abspattern2:
-; DAG: abs.4h
-; DAG-NEXT: ret
-
+; DAG-LABEL: abspattern2:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.4h v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern2:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmgt.4h v1, v0, v1
+; GISEL-NEXT: shl.4h v1, v1, #15
+; GISEL-NEXT: neg.4h v2, v0
+; GISEL-NEXT: sshr.4h v1, v1, #15
+; GISEL-NEXT: bif.8b v0, v2, v1
+; GISEL-NEXT: ret
; For GlobalISel, this generates terrible code until we can pattern match this to abs.
-; GISEL-DAG: neg.4h
-; GISEL-DAG: cmgt.4h
-; GISEL: bif.8b
- %tmp1neg = sub <4 x i16> zeroinitializer, %a
- %b = icmp sgt <4 x i16> %a, zeroinitializer
- %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
- ret <4 x i16> %abs
+
+ %tmp1neg = sub <4 x i16> zeroinitializer, %a
+ %b = icmp sgt <4 x i16> %a, zeroinitializer
+ %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
+ ret <4 x i16> %abs
}
define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
-; CHECK-LABEL: abspattern3:
-; DAG: abs.8b
-; DAG-NEXT: ret
-
-; GISEL-DAG: neg.8b
-; GISEL-DAG: cmgt.8b
-; GISEL: bit.8b
- %tmp1neg = sub <8 x i8> zeroinitializer, %a
- %b = icmp slt <8 x i8> %a, zeroinitializer
- %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
- ret <8 x i8> %abs
+; DAG-LABEL: abspattern3:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.8b v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern3:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmgt.8b v1, v1, v0
+; GISEL-NEXT: shl.8b v1, v1, #7
+; GISEL-NEXT: neg.8b v2, v0
+; GISEL-NEXT: sshr.8b v1, v1, #7
+; GISEL-NEXT: bit.8b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <8 x i8> zeroinitializer, %a
+ %b = icmp slt <8 x i8> %a, zeroinitializer
+ %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
+ ret <8 x i8> %abs
}
define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
-; CHECK-LABEL: abspattern4:
-; DAG: abs.4s
-; DAG-NEXT: ret
-
-; GISEL: cmge.4s
-; GISEL: bif.16b
- %tmp1neg = sub <4 x i32> zeroinitializer, %a
- %b = icmp sge <4 x i32> %a, zeroinitializer
- %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
- ret <4 x i32> %abs
+; DAG-LABEL: abspattern4:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.4s v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern4:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmge.4s v1, v0, v1
+; GISEL-NEXT: shl.4s v1, v1, #31
+; GISEL-NEXT: neg.4s v2, v0
+; GISEL-NEXT: sshr.4s v1, v1, #31
+; GISEL-NEXT: bif.16b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <4 x i32> zeroinitializer, %a
+ %b = icmp sge <4 x i32> %a, zeroinitializer
+ %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
+ ret <4 x i32> %abs
}
define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
-; CHECK-LABEL: abspattern5:
-; DAG: abs.8h
-; DAG-NEXT: ret
-
-; GISEL-DAG: cmgt.8h
-; GISEL-DAG: neg.8h
-; GISEL: bif.16b
- %tmp1neg = sub <8 x i16> zeroinitializer, %a
- %b = icmp sgt <8 x i16> %a, zeroinitializer
- %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
- ret <8 x i16> %abs
+; DAG-LABEL: abspattern5:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.8h v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern5:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmgt.8h v1, v0, v1
+; GISEL-NEXT: shl.8h v1, v1, #15
+; GISEL-NEXT: neg.8h v2, v0
+; GISEL-NEXT: sshr.8h v1, v1, #15
+; GISEL-NEXT: bif.16b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <8 x i16> zeroinitializer, %a
+ %b = icmp sgt <8 x i16> %a, zeroinitializer
+ %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
+ ret <8 x i16> %abs
}
define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
-; CHECK-LABEL: abspattern6:
-; DAG: abs.16b
-; DAG-NEXT: ret
-
-; GISEL: cmgt.16b
-; GISEL: bit.16b
- %tmp1neg = sub <16 x i8> zeroinitializer, %a
- %b = icmp slt <16 x i8> %a, zeroinitializer
- %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
- ret <16 x i8> %abs
+; DAG-LABEL: abspattern6:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.16b v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern6:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmgt.16b v1, v1, v0
+; GISEL-NEXT: shl.16b v1, v1, #7
+; GISEL-NEXT: neg.16b v2, v0
+; GISEL-NEXT: sshr.16b v1, v1, #7
+; GISEL-NEXT: bit.16b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <16 x i8> zeroinitializer, %a
+ %b = icmp slt <16 x i8> %a, zeroinitializer
+ %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
+ ret <16 x i8> %abs
}
define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
-; CHECK-LABEL: abspattern7:
-; DAG: abs.2d
-; DAG-NEXT: ret
-
-; GISEL-DAG: neg.2d
-; GISEL-DAG: cmge.2d
-; GISEL: bit.16b
- %tmp1neg = sub <2 x i64> zeroinitializer, %a
- %b = icmp sle <2 x i64> %a, zeroinitializer
- %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
- ret <2 x i64> %abs
+; DAG-LABEL: abspattern7:
+; DAG: // %bb.0:
+; DAG-NEXT: abs.2d v0, v0
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: abspattern7:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v1, #0000000000000000
+; GISEL-NEXT: cmge.2d v1, v1, v0
+; GISEL-NEXT: shl.2d v1, v1, #63
+; GISEL-NEXT: neg.2d v2, v0
+; GISEL-NEXT: sshr.2d v1, v1, #63
+; GISEL-NEXT: bit.16b v0, v2, v1
+; GISEL-NEXT: ret
+
+ %tmp1neg = sub <2 x i64> zeroinitializer, %a
+ %b = icmp sle <2 x i64> %a, zeroinitializer
+ %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
+ ret <2 x i64> %abs
+}
+
+define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
+; DAG-LABEL: uabd_i32:
+; DAG: // %bb.0:
+; DAG-NEXT: sabdl.2d v0, v0, v1
+; DAG-NEXT: ret
+;
+; GISEL-LABEL: uabd_i32:
+; GISEL: // %bb.0:
+; GISEL-NEXT: movi.2d v2, #0000000000000000
+; GISEL-NEXT: ssubl.2d v0, v0, v1
+; GISEL-NEXT: cmgt.2d v1, v2, v0
+; GISEL-NEXT: shl.2d v1, v1, #63
+; GISEL-NEXT: neg.2d v2, v0
+; GISEL-NEXT: sshr.2d v1, v1, #63
+; GISEL-NEXT: bit.16b v0, v2, v1
+; GISEL-NEXT: ret
+ %aext = sext <2 x i32> %a to <2 x i64>
+ %bext = sext <2 x i32> %b to <2 x i64>
+ %ab
diff = sub nsw <2 x i64> %aext, %bext
+ %abcmp = icmp slt <2 x i64> %ab
diff , zeroinitializer
+ %ababs = sub nsw <2 x i64> zeroinitializer, %ab
diff
+ %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %ab
diff
+ ret <2 x i64> %absel
+}
+
+
+define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: uabd_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov x9, d0
+; CHECK-NEXT: fmov x12, d1
+; CHECK-NEXT: asr x10, x9, #63
+; CHECK-NEXT: asr x13, x12, #63
+; CHECK-NEXT: subs x9, x9, x12
+; CHECK-NEXT: mov.d x8, v0[1]
+; CHECK-NEXT: mov.d x11, v1[1]
+; CHECK-NEXT: sbcs x10, x10, x13
+; CHECK-NEXT: asr x12, x8, #63
+; CHECK-NEXT: asr x14, x11, #63
+; CHECK-NEXT: subs x8, x8, x11
+; CHECK-NEXT: sbcs x11, x12, x14
+; CHECK-NEXT: negs x12, x8
+; CHECK-NEXT: ngcs x13, x11
+; CHECK-NEXT: cmp x11, #0 // =0
+; CHECK-NEXT: csel x2, x12, x8, lt
+; CHECK-NEXT: csel x3, x13, x11, lt
+; CHECK-NEXT: negs x8, x9
+; CHECK-NEXT: ngcs x11, x10
+; CHECK-NEXT: cmp x10, #0 // =0
+; CHECK-NEXT: csel x8, x8, x9, lt
+; CHECK-NEXT: csel x1, x11, x10, lt
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: mov.d v0[1], x1
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
+ %aext = sext <2 x i64> %a to <2 x i128>
+ %bext = sext <2 x i64> %b to <2 x i128>
+ %ab
diff = sub nsw <2 x i128> %aext, %bext
+ %abcmp = icmp slt <2 x i128> %ab
diff , zeroinitializer
+ %ababs = sub nsw <2 x i128> zeroinitializer, %ab
diff
+ %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %ab
diff
+ ret <2 x i128> %absel
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
index 9b351f288d17..5f8447b19bb5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -701,6 +701,122 @@ define void @testLowerToUHADD4s(<4 x i32> %src1, <4 x i32> %src2, <4 x i32>* %de
ret void
}
+
+define <4 x i32> @hadd16_sext_asr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
+; CHECK-LABEL: hadd16_sext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: saddl.4s v0, v0, v1
+; CHECK-NEXT: sshr.4s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i16> %src1 to <4 x i32>
+ %zextsrc2 = sext <4 x i16> %src2 to <4 x i32>
+ %add = add <4 x i32> %zextsrc1, %zextsrc2
+ %resulti16 = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %resulti16
+}
+
+define <4 x i32> @hadd16_zext_asr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
+; CHECK-LABEL: hadd16_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uaddl.4s v0, v0, v1
+; CHECK-NEXT: ushr.4s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
+ %zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
+ %add = add <4 x i32> %zextsrc1, %zextsrc2
+ %resulti16 = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %resulti16
+}
+
+define <4 x i32> @hadd16_sext_lsr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
+; CHECK-LABEL: hadd16_sext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: saddl.4s v0, v0, v1
+; CHECK-NEXT: ushr.4s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i16> %src1 to <4 x i32>
+ %zextsrc2 = sext <4 x i16> %src2 to <4 x i32>
+ %add = add <4 x i32> %zextsrc1, %zextsrc2
+ %resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %resulti16
+}
+
+define <4 x i32> @hadd16_zext_lsr(<4 x i16> %src1, <4 x i16> %src2) nounwind {
+; CHECK-LABEL: hadd16_zext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uaddl.4s v0, v0, v1
+; CHECK-NEXT: ushr.4s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
+ %zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
+ %add = add <4 x i32> %zextsrc1, %zextsrc2
+ %resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %resulti16
+}
+
+
+
+define <4 x i64> @hadd32_sext_asr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
+; CHECK-LABEL: hadd32_sext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: saddl.2d v2, v0, v1
+; CHECK-NEXT: saddl2.2d v0, v0, v1
+; CHECK-NEXT: sshr.2d v1, v0, #1
+; CHECK-NEXT: sshr.2d v0, v2, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
+ %zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
+ %add = add <4 x i64> %zextsrc1, %zextsrc2
+ %resulti32 = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
+ ret <4 x i64> %resulti32
+}
+
+define <4 x i64> @hadd32_zext_asr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
+; CHECK-LABEL: hadd32_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uaddl.2d v2, v0, v1
+; CHECK-NEXT: uaddl2.2d v0, v0, v1
+; CHECK-NEXT: ushr.2d v1, v0, #1
+; CHECK-NEXT: ushr.2d v0, v2, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
+ %zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
+ %add = add <4 x i64> %zextsrc1, %zextsrc2
+ %resulti32 = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
+ ret <4 x i64> %resulti32
+}
+
+define <4 x i64> @hadd32_sext_lsr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
+; CHECK-LABEL: hadd32_sext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: saddl.2d v2, v0, v1
+; CHECK-NEXT: saddl2.2d v0, v0, v1
+; CHECK-NEXT: ushr.2d v1, v0, #1
+; CHECK-NEXT: ushr.2d v0, v2, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
+ %zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
+ %add = add <4 x i64> %zextsrc1, %zextsrc2
+ %resulti32 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
+ ret <4 x i64> %resulti32
+}
+
+define <4 x i64> @hadd32_zext_lsr(<4 x i32> %src1, <4 x i32> %src2) nounwind {
+; CHECK-LABEL: hadd32_zext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uaddl.2d v2, v0, v1
+; CHECK-NEXT: uaddl2.2d v0, v0, v1
+; CHECK-NEXT: ushr.2d v1, v0, #1
+; CHECK-NEXT: ushr.2d v0, v2, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
+ %zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
+ %add = add <4 x i64> %zextsrc1, %zextsrc2
+ %resulti32 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
+ ret <4 x i64> %resulti32
+}
+
+
declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/neg-abs.ll b/llvm/test/CodeGen/AArch64/neg-abs.ll
index 3dcb04a8e35f..88cca29ef94e 100644
--- a/llvm/test/CodeGen/AArch64/neg-abs.ll
+++ b/llvm/test/CodeGen/AArch64/neg-abs.ll
@@ -4,8 +4,8 @@
declare i64 @llvm.abs.i64(i64, i1 immarg)
-define i64 at neg_abs(i64 %x) {
-; CHECK-LABEL: neg_abs:
+define i64 @neg_abs64(i64 %x) {
+; CHECK-LABEL: neg_abs64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: cneg x8, x0, mi
@@ -15,3 +15,95 @@ define i64 at neg_abs(i64 %x) {
%neg = sub nsw i64 0, %abs
ret i64 %neg
}
+
+declare i32 @llvm.abs.i32(i32, i1 immarg)
+
+define i32 @neg_abs32(i32 %x) {
+; CHECK-LABEL: neg_abs32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0 // =0
+; CHECK-NEXT: cneg w8, w0, mi
+; CHECK-NEXT: neg w0, w8
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ %neg = sub nsw i32 0, %abs
+ ret i32 %neg
+}
+
+declare i16 @llvm.abs.i16(i16, i1 immarg)
+
+define i16 @neg_abs16(i16 %x) {
+; CHECK-LABEL: neg_abs16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #15, #1
+; CHECK-NEXT: eor w9, w0, w8
+; CHECK-NEXT: sub w0, w8, w9
+; CHECK-NEXT: ret
+ %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
+ %neg = sub nsw i16 0, %abs
+ ret i16 %neg
+}
+
+
+declare i128 @llvm.abs.i128(i128, i1 immarg)
+
+define i128 @neg_abs128(i128 %x) {
+; CHECK-LABEL: neg_abs128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: asr x8, x1, #63
+; CHECK-NEXT: eor x10, x0, x8
+; CHECK-NEXT: eor x9, x1, x8
+; CHECK-NEXT: subs x0, x8, x10
+; CHECK-NEXT: sbcs x1, x8, x9
+; CHECK-NEXT: ret
+ %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
+ %neg = sub nsw i128 0, %abs
+ ret i128 %neg
+}
+
+
+
+define i64 @abs64(i64 %x) {
+; CHECK-LABEL: abs64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0 // =0
+; CHECK-NEXT: cneg x0, x0, mi
+; CHECK-NEXT: ret
+ %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+ ret i64 %abs
+}
+
+define i32 @abs32(i32 %x) {
+; CHECK-LABEL: abs32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #0 // =0
+; CHECK-NEXT: cneg w0, w0, mi
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+define i16 @abs16(i16 %x) {
+; CHECK-LABEL: abs16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sxth w8, w0
+; CHECK-NEXT: cmp w8, #0 // =0
+; CHECK-NEXT: cneg w0, w8, mi
+; CHECK-NEXT: ret
+ %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
+ ret i16 %abs
+}
+
+define i128 @abs128(i128 %x) {
+; CHECK-LABEL: abs128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: negs x8, x0
+; CHECK-NEXT: ngcs x9, x1
+; CHECK-NEXT: cmp x1, #0 // =0
+; CHECK-NEXT: csel x0, x8, x0, lt
+; CHECK-NEXT: csel x1, x9, x1, lt
+; CHECK-NEXT: ret
+ %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
+ ret i128 %abs
+}
+
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